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625d19c1e2
Import commits from upstream Linux replacing some downstream patches.
Move accepted patches from pending-{5.15,6.1} to backport-{5.15,6.1}.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit f631c7bbb1)
120 lines
4.3 KiB
Diff
120 lines
4.3 KiB
Diff
From 7ff82416de8295c61423ef6fd75f052d3837d2f7 Mon Sep 17 00:00:00 2001
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From: Alexander Couzens <lynxis@fe80.eu>
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Date: Wed, 1 Feb 2023 19:23:29 +0100
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Subject: [PATCH 11/13] net: mediatek: sgmii: ensure the SGMII PHY is powered
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down on configuration
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The code expect the PHY to be in power down which is only true after reset.
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Allow changes of the SGMII parameters more than once.
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Only power down when reconfiguring to avoid bouncing the link when there's
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no reason to - based on code from Russell King.
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There are cases when the SGMII_PHYA_PWD register contains 0x9 which
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prevents SGMII from working. The SGMII still shows link but no traffic
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can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
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taken from a good working state of the SGMII interface.
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Fixes: 42c03844e93d ("net-next: mediatek: add support for MediaTek MT7622 SoC")
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Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
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Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
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[ bmork: rebased and squashed into one patch ]
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Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Bjørn Mork <bjorn@mork.no>
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Acked-by: Daniel Golle <daniel@makrotopia.org>
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Tested-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 ++
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drivers/net/ethernet/mediatek/mtk_sgmii.c | 39 +++++++++++++++------
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2 files changed, 30 insertions(+), 11 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -1064,11 +1064,13 @@ struct mtk_soc_data {
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* @regmap: The register map pointing at the range used to setup
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* SGMII modes
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* @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
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+ * @interface: Currently configured interface mode
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* @pcs: Phylink PCS structure
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*/
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struct mtk_pcs {
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struct regmap *regmap;
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u32 ana_rgc3;
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+ phy_interface_t interface;
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struct phylink_pcs pcs;
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};
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -43,11 +43,6 @@ static int mtk_pcs_config(struct phylink
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int advertise, link_timer;
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bool changed, use_an;
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- if (interface == PHY_INTERFACE_MODE_2500BASEX)
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- rgc3 = RG_PHY_SPEED_3_125G;
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- else
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- rgc3 = 0;
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-
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advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
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advertising);
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if (advertise < 0)
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@@ -88,9 +83,22 @@ static int mtk_pcs_config(struct phylink
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bmcr = 0;
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}
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- /* Configure the underlying interface speed */
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- regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
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- RG_PHY_SPEED_3_125G, rgc3);
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+ if (mpcs->interface != interface) {
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+ /* PHYA power down */
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+ regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
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+ SGMII_PHYA_PWD, SGMII_PHYA_PWD);
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+
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+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
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+ rgc3 = RG_PHY_SPEED_3_125G;
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+ else
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+ rgc3 = 0;
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+
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+ /* Configure the underlying interface speed */
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+ regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
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+ RG_PHY_SPEED_3_125G, rgc3);
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+
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+ mpcs->interface = interface;
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+ }
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/* Update the advertisement, noting whether it has changed */
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regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
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@@ -108,9 +116,17 @@ static int mtk_pcs_config(struct phylink
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regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
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SGMII_AN_RESTART | SGMII_AN_ENABLE, bmcr);
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- /* Release PHYA power down state */
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- regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
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- SGMII_PHYA_PWD, 0);
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+ /* Release PHYA power down state
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+ * Only removing bit SGMII_PHYA_PWD isn't enough.
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+ * There are cases when the SGMII_PHYA_PWD register contains 0x9 which
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+ * prevents SGMII from working. The SGMII still shows link but no traffic
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+ * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
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+ * taken from a good working state of the SGMII interface.
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+ * Unknown how much the QPHY needs but it is racy without a sleep.
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+ * Tested on mt7622 & mt7986.
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+ */
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+ usleep_range(50, 100);
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+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
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return changed;
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}
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@@ -171,6 +187,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss,
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return PTR_ERR(ss->pcs[i].regmap);
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ss->pcs[i].pcs.ops = &mtk_pcs_ops;
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+ ss->pcs[i].interface = PHY_INTERFACE_MODE_NA;
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}
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return 0;
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