openwrt/package/boot/uboot-mediatek/patches/003-mt7622-uboot-add-dts-and-config-for-spi-nand.patch
Daniel Golle ed50004319 uboot-mediatek: add support for Linksys E8450
Build U-Boot for the Linksys E8450 in order to have support for UBI.
The loader has a default environment with scripts handling the reset
button as well as fall-back to recovery firmware. If the loader comes
up without a valid environment found in UBI, it will automatically
make sure UBI is formatted and create a new environment and proceed
to load recovery firmware (either from UBI or via TFTP if recovery is
corrupted or unavailable).

If the button is held down during power-on, the yellow status LED
turns on and the bootloader environment is reset to factory defaults.
If the button is released at this point, the recovery firmware (if
existing) is loaded from UBI and booted.
If the button is continously held down even beyond the point that
the yellow LED turned on, the loader will try to load the recovery
firmware via TFTP from server 192.168.1.254, write it to UBI and
boot.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2021-02-28 01:23:48 +00:00

58 lines
1.5 KiB
Diff

From b1b3c3d2ce62872c8dec4a7d645af6b3c565e094 Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Mon, 20 Apr 2020 17:11:32 +0800
Subject: [PATCH 2/3] mt7622 uboot: add dts and config for spi nand
This patch add dts and config for mt7622 spi nand
Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
---
arch/arm/dts/mt7622-rfb.dts | 6 ++++++
arch/arm/dts/mt7622.dtsi | 20 ++++++++++++++++++++
2 files changed, 26 insertions(+)
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -174,6 +174,12 @@
};
};
+&nandc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&snfi_pins>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -53,6 +53,26 @@
#size-cells = <0>;
};
+ nandc: nfi@1100d000 {
+ compatible = "mediatek,mt7622-nfc";
+ reg = <0x1100d000 0x1000>,
+ <0x1100e000 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_NFIECC_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>,
+ <&topckgen CLK_TOP_NFI_INFRA_SEL>,
+ <&topckgen CLK_TOP_UNIVPLL2_D8>;
+ clock-names = "nfi_clk",
+ "ecc_clk",
+ "snfi_clk",
+ "spinfi_sel",
+ "spinfi_parent_50m";
+ nand-ecc-mode = "hw";
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;