mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 06:08:08 +00:00
c4823622d8
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Acked-by: Felix Fietkau <nbd@nbd.name>
33 lines
1.2 KiB
Diff
33 lines
1.2 KiB
Diff
From 15d52c4067b8d8a1d7a002aec41c5e6c0a8678cd Mon Sep 17 00:00:00 2001
|
|
From: Jonas Gorski <jonas.gorski@gmail.com>
|
|
Date: Fri, 23 Sep 2016 13:58:14 +0200
|
|
Subject: [PATCH] clearfog: reset usom onboard 1512 phy
|
|
|
|
Use GPIO19 which is wired to the uSOM phy reset signal in order to reset
|
|
the uSOM's 88E81512 gigabit Ethernet phy.
|
|
|
|
This GPIO is valid on ClearFog rev 2.1 and newer.
|
|
|
|
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
|
|
[jonas.gorski: adapted to upstream u-boot code]
|
|
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
|
---
|
|
board/solidrun/clearfog/clearfog.c | 4 ++++
|
|
1 file changed, 4 insertions(+)
|
|
|
|
--- a/board/solidrun/clearfog/clearfog.c
|
|
+++ b/board/solidrun/clearfog/clearfog.c
|
|
@@ -131,8 +131,12 @@ int board_init(void)
|
|
/* Toggle GPIO41 to reset onboard switch and phy */
|
|
clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
|
|
clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
|
|
+ /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
|
|
+ clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
|
|
+ clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
|
|
mdelay(1);
|
|
setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
|
|
+ setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
|
|
mdelay(10);
|
|
|
|
/* Init I2C IO expanders */
|