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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
123 lines
3.9 KiB
Diff
123 lines
3.9 KiB
Diff
From 69ed990fda6795039a2b5b37d8ad5df785f4d97b Mon Sep 17 00:00:00 2001
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From: Walker Chen <walker.chen@starfivetech.com>
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Date: Wed, 22 Mar 2023 17:48:18 +0800
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Subject: [PATCH 112/122] dmaengine: dw-axi-dmac: Add support for StarFive
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JH7110 DMA
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Add DMA reset operation in device probe and use different configuration
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on CH_CFG registers according to match data. Update all uses of
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of_device_is_compatible with of_device_get_match_data.
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Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
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Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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---
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.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 38 ++++++++++++++++---
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drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
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2 files changed, 34 insertions(+), 5 deletions(-)
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--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
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+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
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@@ -21,10 +21,12 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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+#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/property.h>
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+#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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@@ -46,6 +48,10 @@
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DMA_SLAVE_BUSWIDTH_32_BYTES | \
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DMA_SLAVE_BUSWIDTH_64_BYTES)
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+#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0)
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+#define AXI_DMA_FLAG_HAS_RESETS BIT(1)
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+#define AXI_DMA_FLAG_USE_CFG2 BIT(2)
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+
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static inline void
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axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
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{
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@@ -86,7 +92,8 @@ static inline void axi_chan_config_write
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cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
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config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
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- if (chan->chip->dw->hdata->reg_map_8_channels) {
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+ if (chan->chip->dw->hdata->reg_map_8_channels &&
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+ !chan->chip->dw->hdata->use_cfg2) {
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cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
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config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
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config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
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@@ -1367,11 +1374,12 @@ static int parse_device_properties(struc
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static int dw_probe(struct platform_device *pdev)
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{
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- struct device_node *node = pdev->dev.of_node;
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struct axi_dma_chip *chip;
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struct resource *mem;
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struct dw_axi_dma *dw;
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struct dw_axi_dma_hcfg *hdata;
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+ struct reset_control *resets;
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+ unsigned int flags;
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u32 i;
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int ret;
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@@ -1400,12 +1408,25 @@ static int dw_probe(struct platform_devi
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if (IS_ERR(chip->regs))
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return PTR_ERR(chip->regs);
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- if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
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+ flags = (uintptr_t)of_device_get_match_data(&pdev->dev);
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+ if (flags & AXI_DMA_FLAG_HAS_APB_REGS) {
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chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(chip->apb_regs))
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return PTR_ERR(chip->apb_regs);
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}
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+ if (flags & AXI_DMA_FLAG_HAS_RESETS) {
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+ resets = devm_reset_control_array_get_exclusive(&pdev->dev);
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+ if (IS_ERR(resets))
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+ return PTR_ERR(resets);
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+
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+ ret = reset_control_deassert(resets);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
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+
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chip->core_clk = devm_clk_get(chip->dev, "core-clk");
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if (IS_ERR(chip->core_clk))
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return PTR_ERR(chip->core_clk);
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@@ -1556,8 +1577,15 @@ static const struct dev_pm_ops dw_axi_dm
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};
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static const struct of_device_id dw_dma_of_id_table[] = {
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- { .compatible = "snps,axi-dma-1.01a" },
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- { .compatible = "intel,kmb-axi-dma" },
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+ {
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+ .compatible = "snps,axi-dma-1.01a"
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+ }, {
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+ .compatible = "intel,kmb-axi-dma",
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+ .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS,
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+ }, {
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+ .compatible = "starfive,jh7110-axi-dma",
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+ .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
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+ },
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{}
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};
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MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
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--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
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+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
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@@ -33,6 +33,7 @@ struct dw_axi_dma_hcfg {
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/* Register map for DMAX_NUM_CHANNELS <= 8 */
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bool reg_map_8_channels;
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bool restrict_axi_burst_len;
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+ bool use_cfg2;
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};
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struct axi_dma_chan {
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