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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
142 lines
4.1 KiB
Diff
142 lines
4.1 KiB
Diff
From e97eb58b321b5b25b7d5c40880e6eb133d381581 Mon Sep 17 00:00:00 2001
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From: Jack Zhu <jack.zhu@starfivetech.com>
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Date: Tue, 23 May 2023 16:56:25 +0800
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Subject: [PATCH 079/122] media: cadence: Add support for external dphy
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Add support for external MIPI D-PHY.
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Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
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---
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drivers/media/platform/cadence/cdns-csi2rx.c | 66 +++++++++++++++++---
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1 file changed, 56 insertions(+), 10 deletions(-)
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--- a/drivers/media/platform/cadence/cdns-csi2rx.c
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+++ b/drivers/media/platform/cadence/cdns-csi2rx.c
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@@ -31,6 +31,12 @@
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#define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane) ((plane) << (16 + (llane) * 4))
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#define CSI2RX_STATIC_CFG_LANES_MASK GENMASK(11, 8)
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+#define CSI2RX_DPHY_LANE_CTRL_REG 0x40
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+#define CSI2RX_DPHY_CL_RST BIT(16)
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+#define CSI2RX_DPHY_DL_RST(i) BIT((i) + 12)
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+#define CSI2RX_DPHY_CL_EN BIT(4)
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+#define CSI2RX_DPHY_DL_EN(i) BIT(i)
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+
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#define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100)
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#define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000)
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@@ -105,6 +111,24 @@ static void csi2rx_reset(struct csi2rx_p
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writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG);
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}
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+static int csi2rx_configure_ext_dphy(struct csi2rx_priv *csi2rx)
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+{
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+ union phy_configure_opts opts = { };
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+ int ret;
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+
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+ ret = phy_power_on(csi2rx->dphy);
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+ if (ret)
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+ return ret;
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+
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+ ret = phy_configure(csi2rx->dphy, &opts);
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+ if (ret) {
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+ phy_power_off(csi2rx->dphy);
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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static int csi2rx_start(struct csi2rx_priv *csi2rx)
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{
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unsigned int i;
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@@ -144,6 +168,17 @@ static int csi2rx_start(struct csi2rx_pr
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if (ret)
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goto err_disable_pclk;
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+ /* Enable DPHY clk and data lanes. */
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+ if (csi2rx->dphy) {
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+ reg = CSI2RX_DPHY_CL_EN | CSI2RX_DPHY_CL_RST;
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+ for (i = 0; i < csi2rx->num_lanes; i++) {
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+ reg |= CSI2RX_DPHY_DL_EN(csi2rx->lanes[i] - 1);
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+ reg |= CSI2RX_DPHY_DL_RST(csi2rx->lanes[i] - 1);
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+ }
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+
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+ writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG);
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+ }
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+
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/*
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* Create a static mapping between the CSI virtual channels
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* and the output stream.
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@@ -177,10 +212,22 @@ static int csi2rx_start(struct csi2rx_pr
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goto err_disable_pixclk;
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reset_control_deassert(csi2rx->sys_rst);
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+
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+ if (csi2rx->dphy) {
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+ ret = csi2rx_configure_ext_dphy(csi2rx);
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+ if (ret) {
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+ dev_err(csi2rx->dev,
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+ "Failed to configure external DPHY: %d\n", ret);
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+ goto err_disable_sysclk;
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+ }
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+ }
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+
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clk_disable_unprepare(csi2rx->p_clk);
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return 0;
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+err_disable_sysclk:
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+ clk_disable_unprepare(csi2rx->sys_clk);
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err_disable_pixclk:
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for (; i > 0; i--) {
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reset_control_assert(csi2rx->pixel_rst[i - 1]);
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@@ -213,6 +260,13 @@ static void csi2rx_stop(struct csi2rx_pr
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if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false))
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dev_warn(csi2rx->dev, "Couldn't disable our subdev\n");
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+
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+ if (csi2rx->dphy) {
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+ writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG);
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+
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+ if (phy_power_off(csi2rx->dphy))
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+ dev_warn(csi2rx->dev, "Couldn't power off DPHY\n");
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+ }
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}
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static int csi2rx_s_stream(struct v4l2_subdev *subdev, int enable)
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@@ -328,15 +382,6 @@ static int csi2rx_get_resources(struct c
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return PTR_ERR(csi2rx->dphy);
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}
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- /*
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- * FIXME: Once we'll have external D-PHY support, the check
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- * will need to be removed.
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- */
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- if (csi2rx->dphy) {
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- dev_err(&pdev->dev, "External D-PHY not supported yet\n");
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- return -EINVAL;
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- }
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-
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ret = clk_prepare_enable(csi2rx->p_clk);
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if (ret) {
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dev_err(&pdev->dev, "Couldn't prepare and enable P clock\n");
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@@ -366,7 +411,7 @@ static int csi2rx_get_resources(struct c
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* FIXME: Once we'll have internal D-PHY support, the check
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* will need to be removed.
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*/
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- if (csi2rx->has_internal_dphy) {
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+ if (!csi2rx->dphy && csi2rx->has_internal_dphy) {
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dev_err(&pdev->dev, "Internal D-PHY not supported yet\n");
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return -EINVAL;
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}
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@@ -494,6 +539,7 @@ static int csi2rx_probe(struct platform_
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dev_info(&pdev->dev,
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"Probed CSI2RX with %u/%u lanes, %u streams, %s D-PHY\n",
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csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams,
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+ csi2rx->dphy ? "external" :
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csi2rx->has_internal_dphy ? "internal" : "no");
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return 0;
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