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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
194 lines
6.0 KiB
Diff
194 lines
6.0 KiB
Diff
From 84575863e4cf1a5dd877a11d31115c19004ac36a Mon Sep 17 00:00:00 2001
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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Date: Thu, 18 May 2023 18:12:24 +0800
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Subject: [PATCH 051/122] dt-bindings: clock: Add StarFive JH7110
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System-Top-Group clock and reset generator
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Add bindings for the System-Top-Group clock and reset generator (STGCRG)
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on the JH7110 RISC-V SoC by StarFive Ltd.
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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---
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.../clock/starfive,jh7110-stgcrg.yaml | 82 +++++++++++++++++++
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.../dt-bindings/clock/starfive,jh7110-crg.h | 34 ++++++++
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.../dt-bindings/reset/starfive,jh7110-crg.h | 28 +++++++
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3 files changed, 144 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml
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@@ -0,0 +1,82 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 System-Top-Group Clock and Reset Generator
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+
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+maintainers:
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+ - Xingyu Wu <xingyu.wu@starfivetech.com>
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-stgcrg
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ items:
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+ - description: Main Oscillator (24 MHz)
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+ - description: HIFI4 core
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+ - description: STG AXI/AHB
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+ - description: USB (125 MHz)
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+ - description: CPU Bus
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+ - description: HIFI4 Axi
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+ - description: NOC STG Bus
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+ - description: APB Bus
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+
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+ clock-names:
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+ items:
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+ - const: osc
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+ - const: hifi4_core
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+ - const: stg_axiahb
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+ - const: usb_125m
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+ - const: cpu_bus
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+ - const: hifi4_axi
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+ - const: nocstg_bus
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+ - const: apb_bus
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+
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+ '#clock-cells':
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+ const: 1
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+ description:
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+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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+
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+ '#reset-cells':
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+ const: 1
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+ description:
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+ See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - '#clock-cells'
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+ - '#reset-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/starfive,jh7110-crg.h>
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+
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+ stgcrg: clock-controller@10230000 {
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+ compatible = "starfive,jh7110-stgcrg";
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+ reg = <0x10230000 0x10000>;
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+ clocks = <&osc>,
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+ <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
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+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
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+ <&syscrg JH7110_SYSCLK_USB_125M>,
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+ <&syscrg JH7110_SYSCLK_CPU_BUS>,
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+ <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
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+ <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
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+ <&syscrg JH7110_SYSCLK_APB_BUS>;
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+ clock-names = "osc", "hifi4_core",
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+ "stg_axiahb", "usb_125m",
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+ "cpu_bus", "hifi4_axi",
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+ "nocstg_bus", "apb_bus";
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
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+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
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@@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/*
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* Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
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+ * Copyright 2022 StarFive Technology Co., Ltd.
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*/
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#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
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@@ -224,4 +225,37 @@
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#define JH7110_AONCLK_END 14
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+/* STGCRG clocks */
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+#define JH7110_STGCLK_HIFI4_CLK_CORE 0
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+#define JH7110_STGCLK_USB0_APB 1
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+#define JH7110_STGCLK_USB0_UTMI_APB 2
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+#define JH7110_STGCLK_USB0_AXI 3
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+#define JH7110_STGCLK_USB0_LPM 4
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+#define JH7110_STGCLK_USB0_STB 5
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+#define JH7110_STGCLK_USB0_APP_125 6
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+#define JH7110_STGCLK_USB0_REFCLK 7
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+#define JH7110_STGCLK_PCIE0_AXI_MST0 8
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+#define JH7110_STGCLK_PCIE0_APB 9
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+#define JH7110_STGCLK_PCIE0_TL 10
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+#define JH7110_STGCLK_PCIE1_AXI_MST0 11
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+#define JH7110_STGCLK_PCIE1_APB 12
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+#define JH7110_STGCLK_PCIE1_TL 13
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+#define JH7110_STGCLK_PCIE_SLV_MAIN 14
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+#define JH7110_STGCLK_SEC_AHB 15
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+#define JH7110_STGCLK_SEC_MISC_AHB 16
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+#define JH7110_STGCLK_GRP0_MAIN 17
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+#define JH7110_STGCLK_GRP0_BUS 18
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+#define JH7110_STGCLK_GRP0_STG 19
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+#define JH7110_STGCLK_GRP1_MAIN 20
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+#define JH7110_STGCLK_GRP1_BUS 21
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+#define JH7110_STGCLK_GRP1_STG 22
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+#define JH7110_STGCLK_GRP1_HIFI 23
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+#define JH7110_STGCLK_E2_RTC 24
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+#define JH7110_STGCLK_E2_CORE 25
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+#define JH7110_STGCLK_E2_DBG 26
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+#define JH7110_STGCLK_DMA1P_AXI 27
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+#define JH7110_STGCLK_DMA1P_AHB 28
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+
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+#define JH7110_STGCLK_END 29
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+
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#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
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--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
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+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
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@@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/*
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
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@@ -151,4 +152,31 @@
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#define JH7110_AONRST_END 8
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+/* STGCRG resets */
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+#define JH7110_STGRST_SYSCON 0
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+#define JH7110_STGRST_HIFI4_CORE 1
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+#define JH7110_STGRST_HIFI4_AXI 2
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+#define JH7110_STGRST_SEC_AHB 3
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+#define JH7110_STGRST_E24_CORE 4
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+#define JH7110_STGRST_DMA1P_AXI 5
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+#define JH7110_STGRST_DMA1P_AHB 6
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+#define JH7110_STGRST_USB0_AXI 7
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+#define JH7110_STGRST_USB0_APB 8
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+#define JH7110_STGRST_USB0_UTMI_APB 9
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+#define JH7110_STGRST_USB0_PWRUP 10
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+#define JH7110_STGRST_PCIE0_AXI_MST0 11
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+#define JH7110_STGRST_PCIE0_AXI_SLV0 12
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+#define JH7110_STGRST_PCIE0_AXI_SLV 13
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+#define JH7110_STGRST_PCIE0_BRG 14
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+#define JH7110_STGRST_PCIE0_CORE 15
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+#define JH7110_STGRST_PCIE0_APB 16
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+#define JH7110_STGRST_PCIE1_AXI_MST0 17
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+#define JH7110_STGRST_PCIE1_AXI_SLV0 18
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+#define JH7110_STGRST_PCIE1_AXI_SLV 19
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+#define JH7110_STGRST_PCIE1_BRG 20
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+#define JH7110_STGRST_PCIE1_CORE 21
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+#define JH7110_STGRST_PCIE1_APB 22
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+
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+#define JH7110_STGRST_END 23
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+
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#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
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