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3774f3272e
The company Zyxel rebranded some years ago. Currently the casing is according to the old branding even for newer devices which already use the new branding. This commit aligns the casing of Zyxel everywhere. Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com> Link: https://github.com/openwrt/openwrt/pull/15652 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
304 lines
10 KiB
Diff
304 lines
10 KiB
Diff
From 3f7be04a148d23cdb5fd320e0e2923983f8bd1f4 Mon Sep 17 00:00:00 2001
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From: Luka Perkov <luka@openwrt.org>
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Date: Tue, 6 Aug 2013 22:51:00 +0200
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Subject: MIPS: add board support for Zyxel P-2812HNU-Fx
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Signed-off-by: Luka Perkov <luka@openwrt.org>
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--- /dev/null
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+++ b/board/zyxel/p2812hnufx/Makefile
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@@ -0,0 +1,27 @@
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+#
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+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
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+#
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+
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+include $(TOPDIR)/config.mk
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+
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+LIB = $(obj)lib$(BOARD).o
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+
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+COBJS = $(BOARD).o
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+
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+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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+OBJS := $(addprefix $(obj),$(COBJS))
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+SOBJS := $(addprefix $(obj),$(SOBJS))
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+
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+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
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+
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+#########################################################################
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+
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+# defines $(obj).depend target
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+include $(SRCTREE)/rules.mk
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+
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+sinclude $(obj).depend
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+
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+#########################################################################
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--- /dev/null
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+++ b/board/zyxel/p2812hnufx/config.mk
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@@ -0,0 +1,7 @@
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+#
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+# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
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+#
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+
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+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
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--- /dev/null
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+++ b/board/zyxel/p2812hnufx/ddr_settings.h
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@@ -0,0 +1,70 @@
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+/*
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+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
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+ *
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+ * The values have been extracted from original Zyxel U-Boot.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#define MC_CCR00_VALUE 0x101
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+#define MC_CCR01_VALUE 0x1000100
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+#define MC_CCR02_VALUE 0x1010000
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+#define MC_CCR03_VALUE 0x101
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+#define MC_CCR04_VALUE 0x1000000
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+#define MC_CCR05_VALUE 0x1000101
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+#define MC_CCR06_VALUE 0x1000100
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+#define MC_CCR07_VALUE 0x1010000
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+#define MC_CCR08_VALUE 0x1000101
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+#define MC_CCR09_VALUE 0x0
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+#define MC_CCR10_VALUE 0x2000100
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+#define MC_CCR11_VALUE 0x2000300
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+#define MC_CCR12_VALUE 0x30000
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+#define MC_CCR13_VALUE 0x202
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+#define MC_CCR14_VALUE 0x7080A0F
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+#define MC_CCR15_VALUE 0x2040F
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+#define MC_CCR16_VALUE 0x40000
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+#define MC_CCR17_VALUE 0x70102
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+#define MC_CCR18_VALUE 0x4020002
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+#define MC_CCR19_VALUE 0x30302
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+#define MC_CCR20_VALUE 0x8000700
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+#define MC_CCR21_VALUE 0x40F020A
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+#define MC_CCR22_VALUE 0x0
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+#define MC_CCR23_VALUE 0xC020000
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+#define MC_CCR24_VALUE 0x4401B04
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+#define MC_CCR25_VALUE 0x0
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+#define MC_CCR26_VALUE 0x0
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+#define MC_CCR27_VALUE 0x6420000
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+#define MC_CCR28_VALUE 0x0
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+#define MC_CCR29_VALUE 0x0
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+#define MC_CCR30_VALUE 0x798
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+#define MC_CCR31_VALUE 0x0
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+#define MC_CCR32_VALUE 0x0
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+#define MC_CCR33_VALUE 0x650000
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+#define MC_CCR34_VALUE 0x200C8
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+#define MC_CCR35_VALUE 0x1D445D
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+#define MC_CCR36_VALUE 0xC8
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+#define MC_CCR37_VALUE 0xC351
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+#define MC_CCR38_VALUE 0x0
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+#define MC_CCR39_VALUE 0x141F04
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+#define MC_CCR40_VALUE 0x142704
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+#define MC_CCR41_VALUE 0x141B42
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+#define MC_CCR42_VALUE 0x141B42
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+#define MC_CCR43_VALUE 0x566504
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+#define MC_CCR44_VALUE 0x566504
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+#define MC_CCR45_VALUE 0x565F17
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+#define MC_CCR46_VALUE 0x565F17
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+#define MC_CCR47_VALUE 0x0
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+#define MC_CCR48_VALUE 0x0
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+#define MC_CCR49_VALUE 0x0
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+#define MC_CCR50_VALUE 0x0
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+#define MC_CCR51_VALUE 0x0
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+#define MC_CCR52_VALUE 0x133
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+#define MC_CCR53_VALUE 0xF3014B27
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+#define MC_CCR54_VALUE 0xF3014B27
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+#define MC_CCR55_VALUE 0xF3014B27
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+#define MC_CCR56_VALUE 0xF3014B27
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+#define MC_CCR57_VALUE 0x7800301
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+#define MC_CCR58_VALUE 0x7800301
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+#define MC_CCR59_VALUE 0x7800301
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+#define MC_CCR60_VALUE 0x7800301
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+#define MC_CCR61_VALUE 0x4
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--- /dev/null
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+++ b/board/zyxel/p2812hnufx/p2812hnufx.c
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@@ -0,0 +1,97 @@
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+/*
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+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <common.h>
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+#include <asm/gpio.h>
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+#include <asm/lantiq/eth.h>
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+#include <asm/lantiq/chipid.h>
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+#include <asm/lantiq/cpu.h>
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+#include <asm/arch/gphy.h>
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+
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+#if defined(CONFIG_SPL_BUILD)
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+#define do_gpio_init 1
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+#define do_pll_init 1
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+#define do_dcdc_init 0
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+#elif defined(CONFIG_SYS_BOOT_RAM)
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+#define do_gpio_init 1
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+#define do_pll_init 0
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+#define do_dcdc_init 1
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+#else
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+#define do_gpio_init 0
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+#define do_pll_init 0
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+#define do_dcdc_init 1
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+#endif
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+
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+static void gpio_init(void)
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+{
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+ /* EBU.FL_CS1 as output for NAND CE */
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+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
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+ /* EBU.FL_A23 as output for NAND CLE */
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+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
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+ /* EBU.FL_A24 as output for NAND ALE */
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+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
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+ /* GPIO 3.0 as input for NAND Ready Busy */
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+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
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+ /* GPIO 3.1 as output for NAND Read */
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+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
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+}
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+
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+int board_early_init_f(void)
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+{
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+ if (do_gpio_init)
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+ gpio_init();
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+
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+ if (do_pll_init)
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+ ltq_pll_init();
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+
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+ if (do_dcdc_init)
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+ ltq_dcdc_init(0x7F);
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+
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+ return 0;
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+}
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+
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+int checkboard(void)
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+{
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+ puts("Board: " CONFIG_BOARD_NAME "\n");
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+ ltq_chip_print_info();
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+
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+ return 0;
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+}
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+
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+static const struct ltq_eth_port_config eth_port_config[] = {
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+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
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+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
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+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
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+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
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+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
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+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
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+ /* GMAC3: unused */
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+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
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+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
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+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
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+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
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+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
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+};
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+
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+static const struct ltq_eth_board_config eth_board_config = {
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+ .ports = eth_port_config,
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+ .num_ports = ARRAY_SIZE(eth_port_config),
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+};
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+
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+int board_eth_init(bd_t * bis)
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+{
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+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
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+ const ulong fw_addr = 0x80FF0000;
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+
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+ ltq_gphy_phy11g_a1x_load(fw_addr);
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+
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+ ltq_cgu_gphy_clk_src(clk);
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+
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+ ltq_rcu_gphy_boot(0, fw_addr);
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+ ltq_rcu_gphy_boot(1, fw_addr);
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+
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+ return ltq_eth_initialize(ð_board_config);
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+}
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--- a/boards.cfg
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+++ b/boards.cfg
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@@ -527,6 +527,8 @@ Active mips mips32 vrx20
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Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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+Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_nandspl p2812hnufx:SYS_BOOT_NANDSPL Luka Perkov <luka@openwrt.org>
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+Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_ram p2812hnufx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
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Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
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Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
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Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
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--- /dev/null
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+++ b/include/configs/p2812hnufx.h
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@@ -0,0 +1,69 @@
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+/*
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+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#ifndef __CONFIG_H
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+#define __CONFIG_H
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+
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+#define CONFIG_MACH_TYPE "P-2812HNU-Fx"
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+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
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+#define CONFIG_BOARD_NAME "Zyxel P-2812HNU-Fx"
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+
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+/* Configure SoC */
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+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
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+
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+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
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+
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+#define CONFIG_LTQ_SUPPORT_NAND_FLASH /* Have a K9F1G08U0D NAND flash */
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+
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+#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */
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+#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
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+#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
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+
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+#define CONFIG_SYS_NAND_PAGE_COUNT 64
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+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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+#define CONFIG_SYS_NAND_OOBSIZE 64
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+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000
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+
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+#define CONFIG_SYS_DRAM_PROBE
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+
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+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
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+
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+/* Environment */
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+#if defined(CONFIG_SYS_BOOT_NANDSPL)
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+#define CONFIG_ENV_IS_IN_NAND
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+#define CONFIG_ENV_OVERWRITE
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+#define CONFIG_ENV_OFFSET (256 * 1024)
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+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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+#else
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+#define CONFIG_ENV_IS_NOWHERE
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+#endif
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+
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+#define CONFIG_ENV_SIZE (8 * 1024)
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+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
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+
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+/* Console */
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+#define CONFIG_LTQ_ADVANCED_CONSOLE
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+#define CONFIG_BAUDRATE 115200
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+#define CONFIG_CONSOLE_ASC 1
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+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
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+
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+/* Pull in default board configs for Lantiq XWAY VRX200 */
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+#include <asm/lantiq/config.h>
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+#include <asm/arch/config.h>
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+
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+/* Pull in default OpenWrt configs for Lantiq SoC */
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+#include "openwrt-lantiq-common.h"
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+
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+#define CONFIG_ENV_UPDATE_UBOOT_NAND \
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+ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0"
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+
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+#define CONFIG_EXTRA_ENV_SETTINGS \
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+ CONFIG_ENV_LANTIQ_DEFAULTS \
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+ CONFIG_ENV_UPDATE_UBOOT_NAND
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+
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+#endif /* __CONFIG_H */
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