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https://github.com/openwrt/openwrt.git
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59 lines
2.0 KiB
Diff
59 lines
2.0 KiB
Diff
diff --git a/drivers/net/pcs/pcs-mtk-usxgmii.c b/drivers/net/pcs/pcs-mtk-usxgmii.c
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index 9af9035..9caab92 100644
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--- a/drivers/net/pcs/pcs-mtk-usxgmii.c
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+++ b/drivers/net/pcs/pcs-mtk-usxgmii.c
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@@ -52,6 +52,12 @@
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#define USXGMII_LPA GENMASK(15, 0)
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#define USXGMII_LPA_LATCH BIT(31)
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+/* Register to control PCS polarity */
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+#define RG_PHY_TOP_CTRL0 0x82C
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+#define USXGMII_PN_SWAP_MASK GENMASK(1, 0)
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+#define USXGMII_PN_SWAP_RX BIT(1)
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+#define USXGMII_PN_SWAP_TX BIT(0)
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+
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/* Register to read PCS link status */
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#define RG_PCS_RX_STATUS0 0x904
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#define RG_PCS_RX_STATUS_UPDATE BIT(16)
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@@ -74,6 +80,7 @@ struct mtk_usxgmii_pcs {
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struct clk *clk;
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struct reset_control *reset;
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phy_interface_t interface;
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+ unsigned int polarity;
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unsigned int neg_mode;
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struct list_head node;
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};
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@@ -155,6 +162,10 @@ static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode
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mtk_usxgmii_reset(mpcs);
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+ /* Configure the interface polarity */
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+ mtk_m32(mpcs, RG_PHY_TOP_CTRL0,
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+ USXGMII_PN_SWAP_MASK, mpcs->polarity);
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+
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/* Setup USXGMII AN ctrl */
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mtk_m32(mpcs, RG_PCS_AN_CTRL0,
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USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
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@@ -332,6 +343,7 @@ static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
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static int mtk_usxgmii_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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+ struct device_node *np = dev->of_node;
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struct mtk_usxgmii_pcs *mpcs;
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mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
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@@ -342,6 +354,13 @@ static int mtk_usxgmii_probe(struct platform_device *pdev)
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if (IS_ERR(mpcs->base))
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return PTR_ERR(mpcs->base);
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+ if (of_property_read_bool(np->parent, "mediatek,pnswap"))
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+ mpcs->polarity = USXGMII_PN_SWAP_TX | USXGMII_PN_SWAP_RX;
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+ else if (of_property_read_bool(np, "mediatek,pnswap-tx"))
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+ mpcs->polarity = USXGMII_PN_SWAP_TX;
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+ else if (of_property_read_bool(np, "mediatek,pnswap-rx"))
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+ mpcs->polarity = USXGMII_PN_SWAP_RX;
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+
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mpcs->dev = dev;
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mpcs->pcs.ops = &mtk_usxgmii_pcs_ops;
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mpcs->pcs.poll = true;
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