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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
53 lines
2.1 KiB
Diff
53 lines
2.1 KiB
Diff
From 1bfcec16a591622b4993c043e6cc4d07f3690767 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sun, 8 Jan 2023 13:39:55 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq8074: correct USB3 QMP PHY-s clock
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output names
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It seems that clock-output-names for the USB3 QMP PHY-s where set without
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actually checking what is the GCC clock driver expecting, so clock core
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could never actually find the parents for usb0_pipe_clk_src and
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usb1_pipe_clk_src clocks in the GCC driver.
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So, correct the names to be what the driver expects so that parenting
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works.
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Before:
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gcc_usb0_pipe_clk_src 0 0 0 125000000 0 0 50000 Y
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gcc_usb1_pipe_clk_src 0 0 0 125000000 0 0 50000 Y
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After:
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usb3phy_0_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y
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usb0_pipe_clk_src 1 1 0 125000000 0 0 50000 Y
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gcc_usb0_pipe_clk 1 1 0 125000000 0 0 50000 Y
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usb3phy_1_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y
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usb1_pipe_clk_src 1 1 0 125000000 0 0 50000 Y
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gcc_usb1_pipe_clk 1 1 0 125000000 0 0 50000 Y
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Fixes: 5e09bc51d07b ("arm64: dts: ipq8074: enable USB support")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -263,7 +263,7 @@
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#clock-cells = <0>;
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clocks = <&gcc GCC_USB1_PIPE_CLK>;
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clock-names = "pipe0";
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- clock-output-names = "gcc_usb1_pipe_clk_src";
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+ clock-output-names = "usb3phy_1_cc_pipe_clk";
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};
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};
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@@ -306,7 +306,7 @@
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#clock-cells = <0>;
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clocks = <&gcc GCC_USB0_PIPE_CLK>;
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clock-names = "pipe0";
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- clock-output-names = "gcc_usb0_pipe_clk_src";
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+ clock-output-names = "usb3phy_0_cc_pipe_clk";
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};
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};
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