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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
44 lines
1.4 KiB
Diff
44 lines
1.4 KiB
Diff
From fb1f6850be00d8dd8a54017be4c1336e224069ac Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 16 Nov 2022 22:26:25 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq8074: use msi-parent for PCIe
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Instead of hardcoding the IRQ, simply use msi-parent instead.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 +++-----
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1 file changed, 3 insertions(+), 5 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -699,7 +699,7 @@
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reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
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ranges = <0 0xb00a000 0xffd>;
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- v2m@0 {
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+ gic_v2m0: v2m@0 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0xffd>;
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@@ -813,8 +813,7 @@
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<0x82000000 0 0x10220000 0x10220000
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0 0xfde0000>; /* non-prefetchable memory */
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- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "msi";
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+ msi-parent = <&gic_v2m0>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 142
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@@ -877,8 +876,7 @@
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<0x82000000 0 0x20220000 0x20220000
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0 0xfde0000>; /* non-prefetchable memory */
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- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "msi";
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+ msi-parent = <&gic_v2m0>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 75
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