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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
38 lines
1.3 KiB
Diff
38 lines
1.3 KiB
Diff
From 8f63346a74c8b3e37ffab2c7a2ddb3c08793dcc2 Mon Sep 17 00:00:00 2001
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From: Johan Hovold <johan+linaro@kernel.org>
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Date: Thu, 15 Sep 2022 16:34:30 +0200
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Subject: [PATCH] arm64: dts: qcom: ipq8074: fix PCIe PHY serdes size
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The size of the PCIe PHY serdes register region is 0x1c4 and the
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corresponding 'reg' property should specifically not include the
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adjacent regions that are defined in the child node (e.g. tx and rx).
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Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
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Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20220915143431.19842-1-johan+linaro@kernel.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -199,7 +199,7 @@
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pcie_qmp0: phy@86000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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- reg = <0x00086000 0x1000>;
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+ reg = <0x00086000 0x1c4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@@ -227,7 +227,7 @@
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pcie_qmp1: phy@8e000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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- reg = <0x0008e000 0x1000>;
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+ reg = <0x0008e000 0x1c4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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