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f4e5880d0f
- removed upstreamed patches - 0901-spansion_nand_id_fix.patch is disabled, not clear if it's needed Signed-off-by: Roman Yeryomin <roman@advem.lv> Signed-off-by: John Crispin <john@phrozen.org>
218 lines
5.6 KiB
Diff
218 lines
5.6 KiB
Diff
From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 7 Dec 2015 17:16:50 +0100
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Subject: [PATCH 52/53] pwm: add mediatek support
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/pwm/Kconfig | 9 +++
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drivers/pwm/Makefile | 1 +
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drivers/pwm/pwm-mediatek.c | 173 ++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 183 insertions(+)
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create mode 100644 drivers/pwm/pwm-mediatek.c
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--- a/drivers/pwm/Kconfig
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+++ b/drivers/pwm/Kconfig
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@@ -302,6 +302,15 @@ config PWM_MEDIATEK
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To compile this driver as a module, choose M here: the module
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will be called pwm-mediatek.
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+config PWM_MEDIATEK_RAMIPS
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+ tristate "Mediatek PWM support"
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+ depends on RALINK && OF
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+ help
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+ Generic PWM framework driver for Mediatek ARM SoC.
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+
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+ To compile this driver as a module, choose M here: the module
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+ will be called pwm-mxs.
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+
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config PWM_MXS
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tristate "Freescale MXS PWM support"
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depends on ARCH_MXS && OF
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--- a/drivers/pwm/Makefile
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+++ b/drivers/pwm/Makefile
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@@ -28,6 +28,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-p
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obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
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obj-$(CONFIG_PWM_MESON) += pwm-meson.o
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obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o
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+obj-$(CONFIG_PWM_MEDIATEK_RAMIPS) += pwm-mediatek-ramips.o
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obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
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obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
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obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
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--- /dev/null
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+++ b/drivers/pwm/pwm-mediatek-ramips.c
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@@ -0,0 +1,173 @@
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+/*
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+ * Mediatek Pulse Width Modulator driver
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+ *
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+ * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/ioport.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/platform_device.h>
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+#include <linux/pwm.h>
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+#include <linux/slab.h>
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+#include <linux/types.h>
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+
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+#define NUM_PWM 4
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+
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+/* PWM registers and bits definitions */
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+#define PWMCON 0x00
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+#define PWMHDUR 0x04
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+#define PWMLDUR 0x08
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+#define PWMGDUR 0x0c
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+#define PWMWAVENUM 0x28
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+#define PWMDWIDTH 0x2c
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+#define PWMTHRES 0x30
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+
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+/**
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+ * struct mtk_pwm_chip - struct representing pwm chip
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+ *
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+ * @mmio_base: base address of pwm chip
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+ * @chip: linux pwm chip representation
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+ */
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+struct mtk_pwm_chip {
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+ void __iomem *mmio_base;
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+ struct pwm_chip chip;
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+};
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+
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+static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
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+{
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+ return container_of(chip, struct mtk_pwm_chip, chip);
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+}
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+
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+static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
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+ unsigned long offset)
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+{
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+ return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
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+}
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+
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+static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
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+ unsigned int num, unsigned long offset,
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+ unsigned long val)
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+{
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+ iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
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+}
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+
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+static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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+ int duty_ns, int period_ns)
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+{
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+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
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+ u32 resolution = 100 / 4;
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+ u32 clkdiv = 0;
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+
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+ while (period_ns / resolution > 8191) {
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+ clkdiv++;
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+ resolution *= 2;
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+ }
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+
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+ if (clkdiv > 7)
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+ return -1;
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+
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+ mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
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+ mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
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+ mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
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+ return 0;
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+}
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+
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+static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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+{
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+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
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+ u32 val;
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+
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+ val = ioread32(pc->mmio_base);
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+ val |= BIT(pwm->hwpwm);
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+ iowrite32(val, pc->mmio_base);
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+
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+ return 0;
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+}
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+
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+static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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+{
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+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
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+ u32 val;
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+
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+ val = ioread32(pc->mmio_base);
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+ val &= ~BIT(pwm->hwpwm);
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+ iowrite32(val, pc->mmio_base);
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+}
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+
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+static const struct pwm_ops mtk_pwm_ops = {
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+ .config = mtk_pwm_config,
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+ .enable = mtk_pwm_enable,
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+ .disable = mtk_pwm_disable,
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+ .owner = THIS_MODULE,
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+};
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+
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+static int mtk_pwm_probe(struct platform_device *pdev)
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+{
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+ struct mtk_pwm_chip *pc;
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+ struct resource *r;
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+ int ret;
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+
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+ pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
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+ if (!pc)
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+ return -ENOMEM;
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+
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+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
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+ if (IS_ERR(pc->mmio_base))
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+ return PTR_ERR(pc->mmio_base);
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+
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+ platform_set_drvdata(pdev, pc);
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+
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+ pc->chip.dev = &pdev->dev;
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+ pc->chip.ops = &mtk_pwm_ops;
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+ pc->chip.base = -1;
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+ pc->chip.npwm = NUM_PWM;
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+
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+ ret = pwmchip_add(&pc->chip);
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+ if (ret < 0)
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+ dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
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+
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+ return ret;
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+}
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+
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+static int mtk_pwm_remove(struct platform_device *pdev)
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+{
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+ struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
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+ int i;
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+
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+ for (i = 0; i < NUM_PWM; i++)
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+ pwm_disable(&pc->chip.pwms[i]);
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+
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+ return pwmchip_remove(&pc->chip);
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+}
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+
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+static const struct of_device_id mtk_pwm_of_match[] = {
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+ { .compatible = "mediatek,mt7628-pwm" },
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+ { }
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+};
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+
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+MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
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+
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+static struct platform_driver mtk_pwm_driver = {
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+ .driver = {
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+ .name = "mtk-pwm",
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+ .owner = THIS_MODULE,
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+ .of_match_table = mtk_pwm_of_match,
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+ },
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+ .probe = mtk_pwm_probe,
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+ .remove = mtk_pwm_remove,
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+};
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+
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+module_platform_driver(mtk_pwm_driver);
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+
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+MODULE_LICENSE("GPL");
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+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
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+MODULE_ALIAS("platform:mtk-pwm");
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