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dce3b0057b
v4.9 CM code has a few bugs on this HW. Disable the GCR register access during boot. This caused a cpu stall. Signed-off-by: John Crispin <john@phrozen.org>
22 lines
783 B
Diff
22 lines
783 B
Diff
Index: linux-4.9.14/arch/mips/kernel/mips-cm.c
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===================================================================
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--- linux-4.9.14.orig/arch/mips/kernel/mips-cm.c
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+++ linux-4.9.14/arch/mips/kernel/mips-cm.c
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@@ -239,6 +239,7 @@ int mips_cm_probe(void)
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/* disable CM regions */
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write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
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+ /*
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write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
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write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
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write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
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@@ -246,7 +247,7 @@ int mips_cm_probe(void)
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write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
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write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
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write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
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-
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+*/
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/* probe for an L2-only sync region */
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mips_cm_probe_l2sync();
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