mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 09:12:39 +00:00
115 lines
4.0 KiB
Diff
115 lines
4.0 KiB
Diff
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
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+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
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@@ -17,6 +17,7 @@
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#define SYSC_REG_CHIP_NAME0 0x00
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#define SYSC_REG_CHIP_NAME1 0x04
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+#define SYSC_REG_EFUSE_CFG 0x08
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#define SYSC_REG_CHIP_REV 0x0c
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#define SYSC_REG_SYSTEM_CONFIG0 0x10
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#define SYSC_REG_SYSTEM_CONFIG1 0x14
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -43,6 +43,9 @@
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#define CLKCFG_FFRAC_MASK 0x001f
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#define CLKCFG_FFRAC_USB_VAL 0x0003
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+/* EFUSE bits */
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+#define EFUSE_MT7688 0x100000
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+
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/* does the board have sdram or ddram */
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static int dram_type;
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@@ -391,7 +394,7 @@ void __init ralink_clk_init(void)
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#define RINT(x) ((x) / 1000000)
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#define RFRAC(x) (((x) / 1000) % 1000)
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- if (mt762x_soc == MT762X_SOC_MT7628AN) {
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+ if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) {
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if (xtal_rate == MHZ(40))
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cpu_rate = MHZ(580);
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else
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@@ -436,7 +439,8 @@ void __init ralink_clk_init(void)
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ralink_clk_add("10000e00.uart2", periph_rate);
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ralink_clk_add("10180000.wmac", xtal_rate);
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- if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) {
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+ if (IS_ENABLED(CONFIG_USB) &&
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+ (mt762x_soc == MT762X_SOC_MT7620A || mt762x_soc == MT762X_SOC_MT7620N)) {
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/*
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* When the CPU goes into sleep mode, the BUS clock will be too low for
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* USB to function properly
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@@ -533,8 +537,15 @@ void prom_soc_init(struct mt762x_soc_inf
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soc_info->compatible = "ralink,mt7620n-soc";
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}
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} else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
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- mt762x_soc = MT762X_SOC_MT7628AN;
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- name = "MT7628AN";
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+ u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
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+
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+ if (efuse & EFUSE_MT7688) {
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+ mt762x_soc = MT762X_SOC_MT7688;
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+ name = "MT7688";
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+ } else {
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+ mt762x_soc = MT762X_SOC_MT7628AN;
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+ name = "MT7628AN";
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+ }
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soc_info->compatible = "ralink,mt7628an-soc";
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} else {
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panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
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@@ -548,13 +559,13 @@ void prom_soc_init(struct mt762x_soc_inf
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cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
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- if (mt762x_soc == MT762X_SOC_MT7628AN)
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+ if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
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dram_type = ((cfg0&0x00000001) == 0x00000001)?SYSCFG0_DRAM_TYPE_DDR1_MT7628:SYSCFG0_DRAM_TYPE_DDR2_MT7628;
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else
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dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
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soc_info->mem_base = MT7620_DRAM_BASE;
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- if (mt762x_soc == MT762X_SOC_MT7628AN)
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+ if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
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mt7628_dram_init(soc_info);
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else
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mt7620_dram_init(soc_info);
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@@ -567,7 +578,7 @@ void prom_soc_init(struct mt762x_soc_inf
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pr_info("Digital PMU set to %s control\n",
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(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
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- if (mt762x_soc == MT762X_SOC_MT7628AN)
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+ if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
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rt2880_pinmux_data = mt7628an_pinmux_data;
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else
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rt2880_pinmux_data = mt7620a_pinmux_data;
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--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
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+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
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@@ -24,6 +24,7 @@ enum mt762x_soc_type {
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MT762X_SOC_MT7620N,
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MT762X_SOC_MT7621AT,
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MT762X_SOC_MT7628AN,
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+ MT762X_SOC_MT7688,
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};
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extern enum mt762x_soc_type mt762x_soc;
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--- a/drivers/net/ethernet/ralink/esw_rt3052.c
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+++ b/drivers/net/ethernet/ralink/esw_rt3052.c
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@@ -611,7 +611,7 @@ static void esw_hw_init(struct rt305x_es
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rt305x_mii_write(esw, 0, 29, 0x598b);
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/* select local register */
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rt305x_mii_write(esw, 0, 31, 0x8000);
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- } else if (mt762x_soc == MT762X_SOC_MT7628AN) {
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+ } else if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) {
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int i;
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// u32 phy_val;
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u32 val;
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@@ -1042,7 +1042,7 @@ esw_get_port_tr_badgood(struct switch_de
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int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
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u32 reg;
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- if ((mt762x_soc != RT305X_SOC_RT5350) && (mt762x_soc != MT762X_SOC_MT7628AN))
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+ if ((mt762x_soc != RT305X_SOC_RT5350) && (mt762x_soc != MT762X_SOC_MT7628AN) && (mt762x_soc != MT762X_SOC_MT7688))
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return -EINVAL;
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if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
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