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dc51c4355d
The OEM layout for Edgerouter X provides for two 3MB kernel slots. As of linux 6.1 the kernel images no longer fit and as such Edgerouter X builds have been disabled in Main. Revise the layout to make kernel1 slot 6MB and drop kernel2 slot. This patch applies the required changes to the dts file. Signed-off-by: Tim Lunn <tim@feathertop.org> Tested-by: Mauri Sandberg <maukka@ext.kapsi.fi> Link: https://github.com/openwrt/openwrt/pull/15194 Signed-off-by: Petr Štetiar <ynezz@true.cz>
152 lines
2.4 KiB
Plaintext
152 lines
2.4 KiB
Plaintext
#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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aliases {
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label-mac-device = &gmac0;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&gmac0 {
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nvmem-cells = <&macaddr_factory_22 0>;
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nvmem-cell-names = "mac-address";
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label = "dsa";
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};
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&switch0 {
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ports {
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port@0 {
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status = "okay";
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label = "eth0";
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};
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port@1 {
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status = "okay";
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label = "eth1";
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nvmem-cells = <&macaddr_factory_22 1>;
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nvmem-cell-names = "mac-address";
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};
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port@2 {
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status = "okay";
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label = "eth2";
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nvmem-cells = <&macaddr_factory_22 2>;
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nvmem-cell-names = "mac-address";
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};
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port@3 {
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status = "okay";
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label = "eth3";
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nvmem-cells = <&macaddr_factory_22 3>;
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nvmem-cell-names = "mac-address";
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};
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port@4 {
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status = "okay";
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label = "eth4";
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nvmem-cells = <&macaddr_factory_22 4>;
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nvmem-cell-names = "mac-address";
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};
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};
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};
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&nand {
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "u-boot-env";
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reg = <0x80000 0x60000>;
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read-only;
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};
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partition@e0000 {
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label = "factory";
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reg = <0xe0000 0x60000>;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_factory_22: macaddr@22 {
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compatible = "mac-base";
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reg = <0x22 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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partition@140000 {
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label = "kernel";
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reg = <0x140000 0x600000>;
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};
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partition@740000 {
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label = "ubi";
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reg = <0x740000 0xf7c0000>;
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};
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};
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};
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&state_default {
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gpio {
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groups = "uart2", "uart3", "pcie", "jtag";
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function = "gpio";
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};
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};
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&spi0 {
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/*
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* This board has 2Mb spi flash soldered in and visible
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* from manufacturer's firmware.
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* But this SoC shares spi and nand pins,
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* and current driver doesn't handle this sharing well
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*/
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status = "disabled";
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flash@1 {
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compatible = "jedec,spi-nor";
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reg = <1>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "spi";
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reg = <0x0 0x200000>;
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read-only;
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};
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};
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};
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};
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&xhci {
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status = "disabled";
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};
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