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108 lines
3.4 KiB
Diff
108 lines
3.4 KiB
Diff
From d377732c8c9aac14ccb900b65678558b0fb8f0f3 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Date: Thu, 17 Jul 2014 23:26:32 +0200
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Subject: [PATCH 152/153] Revert "MIPS: Delete unused function
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add_temporary_entry."
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This reverts commit d7a887a73dec6c387b02a966a71aac767bbd9ce6.
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Function add_temporary_entry is needed by bcm47xx to support highmem. We
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need to add a temporary entry to check for amount of RAM.
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The only change made in this revert was replacing (ENTER|EXIT)_CRITICAL.
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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Cc: linux-mips@linux-mips.org
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Cc: Hauke Mehrtens <hauke@hauke-m.de>
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Patchwork: https://patchwork.linux-mips.org/patch/7395/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/include/asm/pgtable-32.h | 10 ++++++++
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arch/mips/mm/tlb-r4k.c | 47 ++++++++++++++++++++++++++++++++++++++
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2 files changed, 57 insertions(+)
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--- a/arch/mips/include/asm/pgtable-32.h
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+++ b/arch/mips/include/asm/pgtable-32.h
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@@ -19,6 +19,16 @@
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#include <asm-generic/pgtable-nopmd.h>
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/*
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+ * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
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+ * starting at the top and working down. This is for populating the
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+ * TLB before trap_init() puts the TLB miss handler in place. It
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+ * should be used only for entries matching the actual page tables,
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+ * to prevent inconsistencies.
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+ */
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+extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
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+ unsigned long entryhi, unsigned long pagemask);
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+
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+/*
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* Basically we have the same two-level (which is the logical three level
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* Linux page table layout folded) page tables as the i386. Some day
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* when we have proper page coloring support we can have a 1% quicker
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--- a/arch/mips/mm/tlb-r4k.c
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+++ b/arch/mips/mm/tlb-r4k.c
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@@ -389,6 +389,51 @@ int __init has_transparent_hugepage(void
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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+/*
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+ * Used for loading TLB entries before trap_init() has started, when we
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+ * don't actually want to add a wired entry which remains throughout the
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+ * lifetime of the system
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+ */
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+
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+static int temp_tlb_entry __cpuinitdata;
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+
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+__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
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+ unsigned long entryhi, unsigned long pagemask)
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+{
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+ int ret = 0;
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+ unsigned long flags;
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+ unsigned long wired;
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+ unsigned long old_pagemask;
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+ unsigned long old_ctx;
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+
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+ local_irq_save(flags);
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+ /* Save old context and create impossible VPN2 value */
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+ old_ctx = read_c0_entryhi();
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+ old_pagemask = read_c0_pagemask();
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+ wired = read_c0_wired();
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+ if (--temp_tlb_entry < wired) {
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+ printk(KERN_WARNING
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+ "No TLB space left for add_temporary_entry\n");
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+ ret = -ENOSPC;
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+ goto out;
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+ }
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+
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+ write_c0_index(temp_tlb_entry);
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+ write_c0_pagemask(pagemask);
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+ write_c0_entryhi(entryhi);
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+ write_c0_entrylo0(entrylo0);
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+ write_c0_entrylo1(entrylo1);
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+ mtc0_tlbw_hazard();
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+ tlb_write_indexed();
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+ tlbw_use_hazard();
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+
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+ write_c0_entryhi(old_ctx);
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+ write_c0_pagemask(old_pagemask);
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+out:
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+ local_irq_restore(flags);
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+ return ret;
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+}
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+
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static int __cpuinitdata ntlb;
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static int __init set_ntlb(char *str)
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{
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@@ -426,6 +471,8 @@ void __cpuinit tlb_init(void)
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write_c0_pagegrain(pg);
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}
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+ temp_tlb_entry = current_cpu_data.tlbsize - 1;
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+
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/* From this point on the ARC firmware is dead. */
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local_flush_tlb_all();
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