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255a680a99
http://patchwork.ozlabs.org/patch/431024/ Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 44086
149 lines
5.6 KiB
Diff
149 lines
5.6 KiB
Diff
From patchwork Tue Jan 20 11:28:45 2015
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Subject: [OpenWrt-Devel] uboot-lantiq cgu settings for ramboot image
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From: Ben Mulvihill <ben.mulvihill@gmail.com>
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X-Patchwork-Id: 431024
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Message-Id: <1421753325.25187.58.camel@merveille.lan>
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To: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Cc: OpenWrt Development List <openwrt-devel@lists.openwrt.org>
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Date: Tue, 20 Jan 2015 12:28:45 +0100
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On Tue, 2015-01-20 at 00:39 +0100, Ben Mulvihill wrote:
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> On Mon, 2015-01-19 at 19:21 +0100, Ben Mulvihill wrote:
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> > On Mon, 2015-01-19 at 16:47 +0100, Daniel Schwierzeck wrote:
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> > > 2015-01-19 15:44 GMT+01:00 Ben Mulvihill <ben.mulvihill@gmail.com>:
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> > > > On Mon, 2015-01-19 at 11:51 +0000, Conor O'Gorman wrote:
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> > > >> On 19/01/15 10:46, Ben Mulvihill wrote:
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> > > >> > Hello,
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> > > >> >
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> > > >> > I am trying to build uboot-lantiq for the BT Home Hub 3A (lantiq
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> > > >> > ar9), and am wondering where to initialise the cgu, in the case
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> > > >> > of a ramboot image for uart booting. Normally the cgu is initialised
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> > > >> > in lowlevel_init, but that code is bypassed in ramboot images. The
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> > > >> > result is that the board boots with the wrong cgu settings, which
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> > > >> > sends the console haywire. So far I have tried two solutions:
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> > > >>
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> > > >> Another option is to try and not change anything. The console is already
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> > > >> configured and running. The ram does need config.
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> > > >>
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> > > >> I was used to seeing the ramboot version running at half clock speed, at
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> > > >> least on danube, previous to ar9.
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> > > >>
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> > > >> Conor
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> > > >
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> > > > Hi Conor,
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> > > >
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> > > > Thanks for the reply. But with the latest uboot-lantiq, not changing
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> > > > anything means that I don't get a usable console. With an older
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> > > > version I do at least get a uboot console, but no linux console when
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> > > > I boot openwrt. Correcting the cgu settings solves both problems.
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> > > >
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> > >
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> > > could you try this?
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> > >
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> > > diff --git a/arch/mips/cpu/mips32/arx100/cgu.c
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> > > b/arch/mips/cpu/mips32/arx100/cgu.c
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> > > index 6e71ee7..e0afbda 100644
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> > > --- a/arch/mips/cpu/mips32/arx100/cgu.c
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> > > +++ b/arch/mips/cpu/mips32/arx100/cgu.c
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> > > @@ -95,15 +95,5 @@ unsigned long ltq_get_cpu_clock(void)
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> > >
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> > > unsigned long ltq_get_bus_clock(void)
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> > > {
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> > > - u32 fpi_sel;
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> > > - unsigned long clk;
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> > > -
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> > > - fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL);
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> > > -
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> > > - if (fpi_sel)
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> > > - clk = ltq_get_io_region_clock() / 2;
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> > > - else
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> > > - clk = ltq_get_io_region_clock();
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> > > -
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> > > - return clk;
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> > > + return ltq_get_io_region_clock();
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> > > }
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> > >
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> > > the UART driver calculates the baudrate from the FPI bus clock, but
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> > > FPI_SEL is not available on AR9. FPI bus clock is always the same as
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> > > DDR clock, Obviously a copy&paste error from VR9 code ;)
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> > >
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> >
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> > No, even with this patch, I still don't get a working console I'm
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> > afraid. If I don't set anything explicitly, the board comes up with
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> > CGU_SYS set to 0x05, ie CGU_SYS_SYSSEL_PLL0_333_MHZ |
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> > CGU_SYS_CPUSEL_EQUAL_DDRCLK | CGU_SYS_DDRSEL_THIRD_SYSCLK.
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> > Is this a valid combination without CGU_SYS_PPESEL_250_MHZ ?
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> > I don't understand what CGU_SYS_PPESEL_250_MHZ does?
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> > The "right setting", as set by the stock uboot, is 0x80.
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>
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> P.S. There also seems to be a discrepancy between the uboot and
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> linux code. I take it from what you say above that fpi clock, ddr
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> clock and io region clock are all the same. Now if the least
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> significant bit of CGU_SYS is set, then according to the uboot
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> code - function ltq_get_bus_clock() - their value is one
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> third of the system clock. But according to the linux code
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> - function ltq_ar9_fpi_hz() in arch/mips/lantiq/xway/clk.c -
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> their value in this case is equal to the system clock.
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>
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> Or am I getting muddled? It's past my bedtime!
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>
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>
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Some of the bitshifting in arch/mips/cpu/mips32/arx100/cgu.c is 1
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out. A patch along these lines should fix it:
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--- a/arch/mips/cpu/mips32/arx100/cgu.c 2015-01-20 11:57:22.000000000 +0100
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+++ b/arch/mips/cpu/mips32/arx100/cgu.c 2015-01-20 12:00:15.000000000 +0100
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@@ -10,12 +10,17 @@
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#include <asm/lantiq/clk.h>
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#include <asm/lantiq/io.h>
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-#define CGU_SYS_DDR_SEL (1 << 0)
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-#define CGU_SYS_CPU_SEL (1 << 2)
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+#define CGU_SYS_DDR_SHIFT 0
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+#define CGU_SYS_CPU_SHIFT 2
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#define CGU_SYS_SYS_SHIFT 3
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+#define CGU_SYS_FPI_SHIFT 6
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+#define CGU_SYS_PPE_SHIFT 7
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+
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+#define CGU_SYS_DDR_MASK (1 << CGU_SYS_DDR_SHIFT)
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+#define CGU_SYS_CPU_MASK (1 << CGU_SYS_CPU_SHIFT)
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#define CGU_SYS_SYS_MASK (0x3 << CGU_SYS_SYS_SHIFT)
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-#define CGU_SYS_FPI_SEL (1 << 6)
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-#define CGU_SYS_PPE_SEL (1 << 7)
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+#define CGU_SYS_FPI_MASK (1 << CGU_SYS_FPI_SHIFT)
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+#define CGU_SYS_PPE_MASK (1 << CGU_SYS_PPE_SHIFT)
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struct ltq_cgu_regs {
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u32 rsvd0;
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@@ -68,7 +73,7 @@ unsigned long ltq_get_io_region_clock(vo
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u32 ddr_sel;
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unsigned long clk;
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- ddr_sel = ltq_cgu_sys_readl(1, CGU_SYS_DDR_SEL);
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+ ddr_sel = ltq_cgu_sys_readl(CGU_SYS_DDR_MASK, CGU_SYS_DDR_SHIFT);
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if (ddr_sel)
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clk = ltq_get_system_clock() / 3;
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@@ -83,7 +88,7 @@ unsigned long ltq_get_cpu_clock(void)
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u32 cpu_sel;
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unsigned long clk;
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- cpu_sel = ltq_cgu_sys_readl(1, CGU_SYS_CPU_SEL);
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+ cpu_sel = ltq_cgu_sys_readl(CGU_SYS_CPU_MASK, CGU_SYS_CPU_SHIFT);
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if (cpu_sel)
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clk = ltq_get_io_region_clock();
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@@ -98,7 +103,7 @@ unsigned long ltq_get_bus_clock(void)
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u32 fpi_sel;
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unsigned long clk;
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- fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL);
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+ fpi_sel = ltq_cgu_sys_readl(CGU_SYS_FPI_MASK, CGU_SYS_FPI_SHIFT);
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if (fpi_sel)
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clk = ltq_get_io_region_clock() / 2;
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