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9aa196e0f2
Refresh patches, following required reworking: ar71xx/patches-4.9/930-chipidea-pullup.patch layerscape/patches-4.9/302-dts-support-layercape.patch sunxi/patches-4.9/0052-stmmac-form-4-12.patch Fixes for CVEs: CVE-2018-1108 CVE-2018-1092 Tested on: ar71xx Archer C7 v2 Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com> Tested-by: Arjen de Korte <build+openwrt@de-korte.org>
347 lines
9.2 KiB
Diff
347 lines
9.2 KiB
Diff
From 546bac0479e51024027f8c8820f912573643b101 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Wed, 18 Jan 2017 07:31:57 +1100
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Subject: [PATCH] clk: bcm2835: Add leaf clock measurement support, disabled by
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default
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This proved incredibly useful during debugging of the DSI driver, to
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see if our clocks were running at rate we requested. Let's leave it
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here for the next person interacting with clocks on the platform (and
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so that hopefully we can just hook it up to debugfs some day).
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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(cherry picked from commit 3f9195811d8d829556c4cd88d3f9e56a80d5ba60)
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---
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drivers/clk/bcm/clk-bcm2835.c | 144 ++++++++++++++++++++++++++++++++++--------
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1 file changed, 119 insertions(+), 25 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -39,6 +39,7 @@
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#include <linux/clk.h>
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#include <linux/clk/bcm2835.h>
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#include <linux/debugfs.h>
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+#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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@@ -98,7 +99,8 @@
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#define CM_SMIDIV 0x0b4
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/* no definition for 0x0b8 and 0x0bc */
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#define CM_TCNTCTL 0x0c0
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-#define CM_TCNTDIV 0x0c4
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+# define CM_TCNT_SRC1_SHIFT 12
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+#define CM_TCNTCNT 0x0c4
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#define CM_TECCTL 0x0c8
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#define CM_TECDIV 0x0cc
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#define CM_TD0CTL 0x0d0
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@@ -338,6 +340,61 @@ static inline u32 cprman_read(struct bcm
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return readl(cprman->regs + reg);
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}
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+/* Does a cycle of measuring a clock through the TCNT clock, which may
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+ * source from many other clocks in the system.
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+ */
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+static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
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+ u32 tcnt_mux)
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+{
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+ u32 osccount = 19200; /* 1ms */
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+ u32 count;
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+ ktime_t timeout;
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+
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+ spin_lock(&cprman->regs_lock);
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+
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+ cprman_write(cprman, CM_TCNTCTL, CM_KILL);
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+
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+ cprman_write(cprman, CM_TCNTCTL,
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+ (tcnt_mux & CM_SRC_MASK) |
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+ (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);
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+
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+ cprman_write(cprman, CM_OSCCOUNT, osccount);
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+
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+ /* do a kind delay at the start */
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+ mdelay(1);
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+
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+ /* Finish off whatever is left of OSCCOUNT */
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+ timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
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+ while (cprman_read(cprman, CM_OSCCOUNT)) {
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+ if (ktime_after(ktime_get(), timeout)) {
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+ dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
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+ count = 0;
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+ goto out;
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+ }
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+ cpu_relax();
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+ }
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+
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+ /* Wait for BUSY to clear. */
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+ timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
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+ while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
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+ if (ktime_after(ktime_get(), timeout)) {
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+ dev_err(cprman->dev, "timeout waiting for !BUSY\n");
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+ count = 0;
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+ goto out;
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+ }
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+ cpu_relax();
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+ }
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+
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+ count = cprman_read(cprman, CM_TCNTCNT);
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+
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+ cprman_write(cprman, CM_TCNTCTL, 0);
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+
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+out:
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+ spin_unlock(&cprman->regs_lock);
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+
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+ return count * 1000;
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+}
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+
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static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
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struct debugfs_reg32 *regs, size_t nregs,
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struct dentry *dentry)
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@@ -473,6 +530,8 @@ struct bcm2835_clock_data {
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bool is_vpu_clock;
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bool is_mash_clock;
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+
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+ u32 tcnt_mux;
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};
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struct bcm2835_gate_data {
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@@ -1014,6 +1073,17 @@ static int bcm2835_clock_on(struct clk_h
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CM_GATE);
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spin_unlock(&cprman->regs_lock);
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+ /* Debug code to measure the clock once it's turned on to see
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+ * if it's ticking at the rate we expect.
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+ */
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+ if (data->tcnt_mux && false) {
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+ dev_info(cprman->dev,
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+ "clk %s: rate %ld, measure %ld\n",
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+ data->name,
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+ clk_hw_get_rate(hw),
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+ bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
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+ }
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+
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return 0;
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}
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@@ -1780,7 +1850,8 @@ static const struct bcm2835_clk_desc clk
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.ctl_reg = CM_OTPCTL,
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.div_reg = CM_OTPDIV,
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.int_bits = 4,
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- .frac_bits = 0),
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+ .frac_bits = 0,
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+ .tcnt_mux = 6),
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/*
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* Used for a 1Mhz clock for the system clocksource, and also used
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* bythe watchdog timer and the camera pulse generator.
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@@ -1814,13 +1885,15 @@ static const struct bcm2835_clk_desc clk
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.ctl_reg = CM_H264CTL,
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.div_reg = CM_H264DIV,
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.int_bits = 4,
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- .frac_bits = 8),
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+ .frac_bits = 8,
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+ .tcnt_mux = 1),
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[BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
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.name = "isp",
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.ctl_reg = CM_ISPCTL,
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.div_reg = CM_ISPDIV,
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.int_bits = 4,
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- .frac_bits = 8),
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+ .frac_bits = 8,
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+ .tcnt_mux = 2),
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/*
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* Secondary SDRAM clock. Used for low-voltage modes when the PLL
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@@ -1831,13 +1904,15 @@ static const struct bcm2835_clk_desc clk
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.ctl_reg = CM_SDCCTL,
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.div_reg = CM_SDCDIV,
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.int_bits = 6,
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- .frac_bits = 0),
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+ .frac_bits = 0,
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+ .tcnt_mux = 3),
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[BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
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.name = "v3d",
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.ctl_reg = CM_V3DCTL,
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.div_reg = CM_V3DDIV,
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.int_bits = 4,
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- .frac_bits = 8),
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+ .frac_bits = 8,
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+ .tcnt_mux = 4),
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/*
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* VPU clock. This doesn't have an enable bit, since it drives
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* the bus for everything else, and is special so it doesn't need
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@@ -1851,7 +1926,8 @@ static const struct bcm2835_clk_desc clk
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.int_bits = 12,
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.frac_bits = 8,
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.flags = CLK_IS_CRITICAL,
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- .is_vpu_clock = true),
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+ .is_vpu_clock = true,
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+ .tcnt_mux = 5),
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/* clocks with per parent mux */
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[BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
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@@ -1859,19 +1935,22 @@ static const struct bcm2835_clk_desc clk
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.ctl_reg = CM_AVEOCTL,
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.div_reg = CM_AVEODIV,
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.int_bits = 4,
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- .frac_bits = 0),
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+ .frac_bits = 0,
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+ .tcnt_mux = 38),
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[BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
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.name = "cam0",
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.ctl_reg = CM_CAM0CTL,
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.div_reg = CM_CAM0DIV,
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.int_bits = 4,
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- .frac_bits = 8),
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+ .frac_bits = 8,
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+ .tcnt_mux = 14),
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[BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
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.name = "cam1",
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.ctl_reg = CM_CAM1CTL,
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.div_reg = CM_CAM1DIV,
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.int_bits = 4,
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- .frac_bits = 8),
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+ .frac_bits = 8,
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+ .tcnt_mux = 15),
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[BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
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.name = "dft",
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.ctl_reg = CM_DFTCTL,
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@@ -1883,7 +1962,8 @@ static const struct bcm2835_clk_desc clk
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.ctl_reg = CM_DPICTL,
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.div_reg = CM_DPIDIV,
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.int_bits = 4,
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- .frac_bits = 8),
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+ .frac_bits = 8,
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+ .tcnt_mux = 17),
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/* Arasan EMMC clock */
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[BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
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@@ -1891,7 +1971,8 @@ static const struct bcm2835_clk_desc clk
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.ctl_reg = CM_EMMCCTL,
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.div_reg = CM_EMMCDIV,
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.int_bits = 4,
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- .frac_bits = 8),
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+ .frac_bits = 8,
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+ .tcnt_mux = 39),
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/* General purpose (GPIO) clocks */
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[BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
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@@ -1900,7 +1981,8 @@ static const struct bcm2835_clk_desc clk
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.div_reg = CM_GP0DIV,
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.int_bits = 12,
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.frac_bits = 12,
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- .is_mash_clock = true),
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+ .is_mash_clock = true,
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+ .tcnt_mux = 20),
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[BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
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.name = "gp1",
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.ctl_reg = CM_GP1CTL,
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@@ -1908,7 +1990,8 @@ static const struct bcm2835_clk_desc clk
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.int_bits = 12,
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.frac_bits = 12,
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.flags = CLK_IS_CRITICAL,
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- .is_mash_clock = true),
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+ .is_mash_clock = true,
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+ .tcnt_mux = 21),
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[BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
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.name = "gp2",
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.ctl_reg = CM_GP2CTL,
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@@ -1923,40 +2006,46 @@ static const struct bcm2835_clk_desc clk
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.ctl_reg = CM_HSMCTL,
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.div_reg = CM_HSMDIV,
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.int_bits = 4,
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- .frac_bits = 8),
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+ .frac_bits = 8,
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+ .tcnt_mux = 22),
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[BCM2835_CLOCK_PCM] = REGISTER_PER_CLK(
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.name = "pcm",
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.ctl_reg = CM_PCMCTL,
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.div_reg = CM_PCMDIV,
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.int_bits = 12,
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.frac_bits = 12,
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- .is_mash_clock = true),
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+ .is_mash_clock = true,
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+ .tcnt_mux = 23),
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[BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
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.name = "pwm",
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.ctl_reg = CM_PWMCTL,
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.div_reg = CM_PWMDIV,
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.int_bits = 12,
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.frac_bits = 12,
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- .is_mash_clock = true),
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+ .is_mash_clock = true,
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+ .tcnt_mux = 24),
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[BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
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.name = "slim",
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.ctl_reg = CM_SLIMCTL,
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.div_reg = CM_SLIMDIV,
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.int_bits = 12,
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.frac_bits = 12,
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- .is_mash_clock = true),
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+ .is_mash_clock = true,
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+ .tcnt_mux = 25),
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[BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
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.name = "smi",
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.ctl_reg = CM_SMICTL,
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.div_reg = CM_SMIDIV,
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.int_bits = 4,
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- .frac_bits = 8),
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+ .frac_bits = 8,
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+ .tcnt_mux = 27),
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[BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
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.name = "uart",
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.ctl_reg = CM_UARTCTL,
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.div_reg = CM_UARTDIV,
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.int_bits = 10,
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- .frac_bits = 12),
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+ .frac_bits = 12,
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+ .tcnt_mux = 28),
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/* TV encoder clock. Only operating frequency is 108Mhz. */
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[BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
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@@ -1969,7 +2058,8 @@ static const struct bcm2835_clk_desc clk
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* Allow rate change propagation only on PLLH_AUX which is
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* assigned index 7 in the parent array.
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*/
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- .set_rate_parent = BIT(7)),
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+ .set_rate_parent = BIT(7),
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+ .tcnt_mux = 29),
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/* dsi clocks */
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[BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
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@@ -1977,25 +2067,29 @@ static const struct bcm2835_clk_desc clk
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.ctl_reg = CM_DSI0ECTL,
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.div_reg = CM_DSI0EDIV,
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.int_bits = 4,
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- .frac_bits = 8),
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+ .frac_bits = 8,
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+ .tcnt_mux = 18),
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[BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
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.name = "dsi1e",
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.ctl_reg = CM_DSI1ECTL,
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.div_reg = CM_DSI1EDIV,
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.int_bits = 4,
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- .frac_bits = 8),
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+ .frac_bits = 8,
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+ .tcnt_mux = 19),
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[BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
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.name = "dsi0p",
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.ctl_reg = CM_DSI0PCTL,
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.div_reg = CM_DSI0PDIV,
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.int_bits = 0,
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- .frac_bits = 0),
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+ .frac_bits = 0,
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+ .tcnt_mux = 12),
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[BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
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.name = "dsi1p",
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.ctl_reg = CM_DSI1PCTL,
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.div_reg = CM_DSI1PDIV,
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.int_bits = 0,
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- .frac_bits = 0),
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+ .frac_bits = 0,
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+ .tcnt_mux = 13),
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/* the gates */
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