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313197d707
This gets us in sync with dts from kernel 4.11. Two patches were already backported earlier. I decided to use 03x prefix as it's kind of similar to the 3xx prefix: 3xx - architecture specific patches It isn't any documented or strict rule though. We don't need to stick to it if we hit any problems. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Álvaro Fernández Rojas <noltari@gmail.com>
147 lines
4.5 KiB
Diff
147 lines
4.5 KiB
Diff
From 6f92d02f7af5a9b5ed5ded7dbeb18bf2bbb2ad85 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.org>
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Date: Tue, 24 Feb 2015 13:40:50 +0000
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Subject: [PATCH] pinctrl-bcm2835: Fix interrupt handling for GPIOs 28-31 and
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46-53
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Contrary to the documentation, the BCM2835 GPIO controller actually has
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four interrupt lines - one each for the three IRQ groups and one common. Rather
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confusingly, the GPIO interrupt groups don't correspond directly with the GPIO
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control banks. Instead, GPIOs 0-27 generate IRQ GPIO0, 28-45 GPIO1 and
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46-53 GPIO2.
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Awkwardly, the GPIOS for IRQ GPIO1 straddle two 32-entry GPIO banks, so it is
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cleaner to split out a function to process the interrupts for a single GPIO
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bank.
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This bug has only just been observed because GPIOs above 27 can only be
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accessed on an old Raspberry Pi with the optional P5 header fitted, where
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the pins are often used for I2S instead.
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---
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drivers/pinctrl/bcm/pinctrl-bcm2835.c | 51 ++++++++++++++++++++++++++---------
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1 file changed, 39 insertions(+), 12 deletions(-)
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--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
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+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
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@@ -47,6 +47,7 @@
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#define MODULE_NAME "pinctrl-bcm2835"
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#define BCM2835_NUM_GPIOS 54
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#define BCM2835_NUM_BANKS 2
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+#define BCM2835_NUM_IRQS 3
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#define BCM2835_PIN_BITMAP_SZ \
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DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
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@@ -82,13 +83,13 @@ enum bcm2835_pinconf_param {
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struct bcm2835_gpio_irqdata {
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struct bcm2835_pinctrl *pc;
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- int bank;
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+ int irqgroup;
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};
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struct bcm2835_pinctrl {
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struct device *dev;
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void __iomem *base;
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- int irq[BCM2835_NUM_BANKS];
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+ int irq[BCM2835_NUM_IRQS];
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/* note: locking assumes each bank will have its own unsigned long */
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unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
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@@ -99,7 +100,7 @@ struct bcm2835_pinctrl {
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range gpio_range;
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- struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
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+ struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_IRQS];
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spinlock_t irq_lock[BCM2835_NUM_BANKS];
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};
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@@ -385,17 +386,16 @@ static struct gpio_chip bcm2835_gpio_chi
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.can_sleep = false,
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};
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-static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
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+static int bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
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+ unsigned int bank, u32 mask)
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{
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- struct bcm2835_gpio_irqdata *irqdata = dev_id;
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- struct bcm2835_pinctrl *pc = irqdata->pc;
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- int bank = irqdata->bank;
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unsigned long events;
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unsigned offset;
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unsigned gpio;
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unsigned int type;
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events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
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+ events &= mask;
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events &= pc->enabled_irq_map[bank];
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for_each_set_bit(offset, &events, 32) {
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gpio = (32 * bank) + offset;
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@@ -403,7 +403,30 @@ static irqreturn_t bcm2835_gpio_irq_hand
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generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
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}
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- return events ? IRQ_HANDLED : IRQ_NONE;
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+
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+ return (events != 0);
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+}
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+
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+static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
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+{
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+ struct bcm2835_gpio_irqdata *irqdata = dev_id;
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+ struct bcm2835_pinctrl *pc = irqdata->pc;
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+ int handled = 0;
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+
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+ switch (irqdata->irqgroup) {
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+ case 0: /* IRQ0 covers GPIOs 0-27 */
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+ handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
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+ break;
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+ case 1: /* IRQ1 covers GPIOs 28-45 */
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+ handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000) |
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+ bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
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+ break;
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+ case 2: /* IRQ2 covers GPIOs 46-53 */
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+ handled = bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
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+ break;
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+ }
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+
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+ return handled ? IRQ_HANDLED : IRQ_NONE;
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}
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static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
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@@ -992,8 +1015,6 @@ static int bcm2835_pinctrl_probe(struct
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for (i = 0; i < BCM2835_NUM_BANKS; i++) {
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unsigned long events;
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unsigned offset;
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- int len;
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- char *name;
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/* clear event detection flags */
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bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
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@@ -1008,10 +1029,15 @@ static int bcm2835_pinctrl_probe(struct
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for_each_set_bit(offset, &events, 32)
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bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
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+ spin_lock_init(&pc->irq_lock[i]);
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+ }
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+
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+ for (i = 0; i < BCM2835_NUM_IRQS; i++) {
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+ int len;
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+ char *name;
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pc->irq[i] = irq_of_parse_and_map(np, i);
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pc->irq_data[i].pc = pc;
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- pc->irq_data[i].bank = i;
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- spin_lock_init(&pc->irq_lock[i]);
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+ pc->irq_data[i].irqgroup = i;
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len = strlen(dev_name(pc->dev)) + 16;
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name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
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@@ -1068,6 +1094,7 @@ static struct platform_driver bcm2835_pi
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.remove = bcm2835_pinctrl_remove,
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.driver = {
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.name = MODULE_NAME,
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+ .owner = THIS_MODULE,
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.of_match_table = bcm2835_pinctrl_match,
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},
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};
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