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52 lines
1.9 KiB
Diff
52 lines
1.9 KiB
Diff
From 68557a66b206de79a4556d393d51865407525d52 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Mon, 6 May 2013 09:59:00 -0300
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Subject: [PATCH] clk: sunxi: add gating support to PLL1
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This commit adds gating support to PLL1 on the clock driver. This makes
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the PLL1 implementation fully compatible with PLL4 as well.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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---
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Documentation/devicetree/bindings/clock/sunxi.txt | 2 +-
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drivers/clk/sunxi/clk-sunxi.c | 2 ++
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
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index 00a5c264..7d9245f 100644
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--- a/Documentation/devicetree/bindings/clock/sunxi.txt
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+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
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@@ -7,7 +7,7 @@ This binding uses the common clock binding[1].
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Required properties:
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- compatible : shall be one of the following:
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"allwinner,sun4i-osc-clk" - for a gatable oscillator
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- "allwinner,sun4i-pll1-clk" - for the main PLL clock
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+ "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
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"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
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"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
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"allwinner,sun4i-axi-clk" - for the AXI clock
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diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
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index 6aed57f..c0b0675 100644
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -293,11 +293,13 @@ struct factors_data {
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};
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static const struct factors_data sun4i_pll1_data __initconst = {
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+ .enable = 31,
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.table = &sun4i_pll1_config,
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.getter = sun4i_get_pll1_factors,
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};
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static const struct factors_data sun6i_a31_pll1_data __initconst = {
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+ .enable = 31,
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.table = &sun6i_a31_pll1_config,
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.getter = sun6i_a31_get_pll1_factors,
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};
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--
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1.8.4
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