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0e561a2aea
This commit contains a series of fixes for DMA. The burst length patch significantly improves Ethernet performance. Patches were tested on the xRX200 and xRX330. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
42 lines
1.6 KiB
Diff
42 lines
1.6 KiB
Diff
From 7d9ea9052d6680d2910b8b005c397d95b3a8b012 Mon Sep 17 00:00:00 2001
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From: Aleksander Jan Bajkowski <olek2@wp.pl>
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Date: Wed, 7 Apr 2021 21:04:39 +0200
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Subject: [PATCH 3/5] MIPS: lantiq: dma: fix burst length for DEU
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The current definition of 2W burst length is invalid.
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This patch fixes it. Current downstream DEU driver doesn't
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use DMA. An incorrect burst length value doesn't cause any
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errors. This patch also adds other burst length values.
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Fixes: dfec1a827d2b ("MIPS: Lantiq: Add DMA support")
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Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
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---
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arch/mips/lantiq/xway/dma.c | 9 +++++++--
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1 file changed, 7 insertions(+), 2 deletions(-)
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--- a/arch/mips/lantiq/xway/dma.c
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+++ b/arch/mips/lantiq/xway/dma.c
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@@ -40,7 +40,11 @@
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#define DMA_IRQ_ACK 0x7e /* IRQ status register */
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#define DMA_POLL BIT(31) /* turn on channel polling */
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#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
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-#define DMA_2W_BURST BIT(1) /* 2 word burst length */
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+#define DMA_PCTRL_2W_BURST 0x1 /* 2 word burst length */
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+#define DMA_PCTRL_4W_BURST 0x2 /* 4 word burst length */
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+#define DMA_PCTRL_8W_BURST 0x3 /* 8 word burst length */
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+#define DMA_TX_BURST_SHIFT 4 /* tx burst shift */
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+#define DMA_RX_BURST_SHIFT 2 /* rx burst shift */
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#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
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#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
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@@ -191,7 +195,8 @@ ltq_dma_init_port(int p)
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break;
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case DMA_PORT_DEU:
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- ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
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+ ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) |
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+ (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
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LTQ_DMA_PCTRL);
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break;
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