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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64)
81 lines
2.6 KiB
Diff
81 lines
2.6 KiB
Diff
From e2537b383e247198347e7124876b9ead531dbeef Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Fri, 7 Feb 2020 16:14:18 +0100
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Subject: [PATCH] clk: bcm: rpi: Split pllb clock hooks
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The driver only supports the pllb for now and all the clock framework hooks
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are a mix of the generic firmware interface and the specifics of the pllb.
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Since we will support more clocks in the future let's split the generic and
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specific hooks
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Cc: Michael Turquette <mturquette@baylibre.com>
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Cc: linux-clk@vger.kernel.org
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Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/clk/bcm/clk-raspberrypi.c | 30 ++++++++++++++++++++++--------
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1 file changed, 22 insertions(+), 8 deletions(-)
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--- a/drivers/clk/bcm/clk-raspberrypi.c
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+++ b/drivers/clk/bcm/clk-raspberrypi.c
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@@ -104,8 +104,8 @@ static int raspberrypi_fw_is_prepared(st
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}
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-static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
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- unsigned long parent_rate)
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+static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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{
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struct raspberrypi_clk_data *data =
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container_of(hw, struct raspberrypi_clk_data, hw);
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@@ -118,21 +118,27 @@ static unsigned long raspberrypi_fw_pll_
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if (ret)
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return ret;
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- return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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+ return val;
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}
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-static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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- unsigned long parent_rate)
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+static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ return raspberrypi_fw_get_rate(hw, parent_rate) *
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+ RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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+}
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+
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+static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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{
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struct raspberrypi_clk_data *data =
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container_of(hw, struct raspberrypi_clk_data, hw);
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struct raspberrypi_clk *rpi = data->rpi;
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- u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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+ u32 _rate = rate;
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int ret;
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ret = raspberrypi_clock_property(rpi->firmware, data,
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- RPI_FIRMWARE_SET_CLOCK_RATE,
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- &new_rate);
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+ RPI_FIRMWARE_SET_CLOCK_RATE, &_rate);
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if (ret)
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dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d",
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clk_hw_get_name(hw), ret);
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@@ -140,6 +146,14 @@ static int raspberrypi_fw_pll_set_rate(s
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return ret;
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}
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+static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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+
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+ return raspberrypi_fw_set_rate(hw, new_rate, parent_rate);
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+}
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+
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/*
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* Sadly there is no firmware rate rounding interface. We borrowed it from
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* clk-bcm2835.
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