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https://github.com/openwrt/openwrt.git
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d41d9befb9
Add u-boot bootloader based on 2023.01 to support D1-based boards, currently: - Dongshan Nezha STU - LicheePi RV Dock - MangoPi MQ-Pro - Nezha D1 Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
296 lines
11 KiB
Diff
296 lines
11 KiB
Diff
From 2f48dfc23d612f6f1798ff761854fd3141d0671f Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 15 May 2022 21:29:22 -0500
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Subject: [PATCH 27/90] clk: sunxi: Add NAND clocks and resets
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Currently NAND clock setup is done in board code, both in SPL and in
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U-Boot proper. Add the NAND clocks/resets here so they can be used by
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the "full" NAND driver once it is converted to the driver model.
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The bit locations are copied from the Linux CCU drivers.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/clk/sunxi/clk_a10.c | 2 ++
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drivers/clk/sunxi/clk_a10s.c | 2 ++
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drivers/clk/sunxi/clk_a23.c | 3 +++
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drivers/clk/sunxi/clk_a31.c | 6 ++++++
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drivers/clk/sunxi/clk_a64.c | 3 +++
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drivers/clk/sunxi/clk_a80.c | 8 ++++++++
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drivers/clk/sunxi/clk_a83t.c | 3 +++
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drivers/clk/sunxi/clk_h3.c | 3 +++
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drivers/clk/sunxi/clk_h6.c | 6 ++++++
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drivers/clk/sunxi/clk_h616.c | 6 ++++++
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drivers/clk/sunxi/clk_r40.c | 3 +++
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11 files changed, 45 insertions(+)
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--- a/drivers/clk/sunxi/clk_a10.c
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+++ b/drivers/clk/sunxi/clk_a10.c
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@@ -23,6 +23,7 @@ static struct ccu_clk_gate a10_gates[] =
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[CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
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[CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
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[CLK_AHB_MMC3] = GATE(0x060, BIT(11)),
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+ [CLK_AHB_NAND] = GATE(0x060, BIT(13)),
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[CLK_AHB_EMAC] = GATE(0x060, BIT(17)),
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[CLK_AHB_SPI0] = GATE(0x060, BIT(20)),
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[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
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@@ -47,6 +48,7 @@ static struct ccu_clk_gate a10_gates[] =
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[CLK_APB1_UART6] = GATE(0x06c, BIT(22)),
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[CLK_APB1_UART7] = GATE(0x06c, BIT(23)),
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+ [CLK_NAND] = GATE(0x080, BIT(31)),
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[CLK_SPI0] = GATE(0x0a0, BIT(31)),
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[CLK_SPI1] = GATE(0x0a4, BIT(31)),
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[CLK_SPI2] = GATE(0x0a8, BIT(31)),
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--- a/drivers/clk/sunxi/clk_a10s.c
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+++ b/drivers/clk/sunxi/clk_a10s.c
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@@ -20,6 +20,7 @@ static struct ccu_clk_gate a10s_gates[]
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[CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
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[CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
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[CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
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+ [CLK_AHB_NAND] = GATE(0x060, BIT(13)),
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[CLK_AHB_EMAC] = GATE(0x060, BIT(17)),
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[CLK_AHB_SPI0] = GATE(0x060, BIT(20)),
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[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
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@@ -35,6 +36,7 @@ static struct ccu_clk_gate a10s_gates[]
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[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
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[CLK_APB1_UART3] = GATE(0x06c, BIT(19)),
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+ [CLK_NAND] = GATE(0x080, BIT(31)),
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[CLK_SPI0] = GATE(0x0a0, BIT(31)),
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[CLK_SPI1] = GATE(0x0a4, BIT(31)),
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[CLK_SPI2] = GATE(0x0a8, BIT(31)),
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--- a/drivers/clk/sunxi/clk_a23.c
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+++ b/drivers/clk/sunxi/clk_a23.c
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@@ -17,6 +17,7 @@ static struct ccu_clk_gate a23_gates[] =
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[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
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[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
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[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
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+ [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
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[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
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[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
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[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
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@@ -34,6 +35,7 @@ static struct ccu_clk_gate a23_gates[] =
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[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
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[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
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+ [CLK_NAND] = GATE(0x080, BIT(31)),
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[CLK_SPI0] = GATE(0x0a0, BIT(31)),
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[CLK_SPI1] = GATE(0x0a4, BIT(31)),
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@@ -52,6 +54,7 @@ static struct ccu_reset a23_resets[] = {
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[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
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[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
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[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
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+ [RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
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[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
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[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
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[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
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--- a/drivers/clk/sunxi/clk_a31.c
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+++ b/drivers/clk/sunxi/clk_a31.c
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@@ -18,6 +18,8 @@ static struct ccu_clk_gate a31_gates[] =
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[CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
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[CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
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[CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
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+ [CLK_AHB1_NAND1] = GATE(0x060, BIT(12)),
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+ [CLK_AHB1_NAND0] = GATE(0x060, BIT(13)),
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[CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
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[CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
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[CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
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@@ -43,6 +45,8 @@ static struct ccu_clk_gate a31_gates[] =
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[CLK_APB2_UART4] = GATE(0x06c, BIT(20)),
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[CLK_APB2_UART5] = GATE(0x06c, BIT(21)),
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+ [CLK_NAND0] = GATE(0x080, BIT(31)),
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+ [CLK_NAND1] = GATE(0x084, BIT(31)),
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[CLK_SPI0] = GATE(0x0a0, BIT(31)),
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[CLK_SPI1] = GATE(0x0a4, BIT(31)),
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[CLK_SPI2] = GATE(0x0a8, BIT(31)),
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@@ -65,6 +69,8 @@ static struct ccu_reset a31_resets[] = {
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[RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
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[RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
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[RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
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+ [RST_AHB1_NAND1] = RESET(0x2c0, BIT(12)),
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+ [RST_AHB1_NAND0] = RESET(0x2c0, BIT(13)),
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[RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)),
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[RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
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[RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),
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--- a/drivers/clk/sunxi/clk_a64.c
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+++ b/drivers/clk/sunxi/clk_a64.c
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@@ -19,6 +19,7 @@ static const struct ccu_clk_gate a64_gat
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[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
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[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
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[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
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+ [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
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[CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
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[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
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[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
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@@ -39,6 +40,7 @@ static const struct ccu_clk_gate a64_gat
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[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
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[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
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+ [CLK_NAND] = GATE(0x080, BIT(31)),
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[CLK_SPI0] = GATE(0x0a0, BIT(31)),
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[CLK_SPI1] = GATE(0x0a4, BIT(31)),
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@@ -58,6 +60,7 @@ static const struct ccu_reset a64_resets
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[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
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[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
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[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
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+ [RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
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[RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
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[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
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[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
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--- a/drivers/clk/sunxi/clk_a80.c
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+++ b/drivers/clk/sunxi/clk_a80.c
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@@ -14,12 +14,18 @@
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#include <linux/bitops.h>
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static const struct ccu_clk_gate a80_gates[] = {
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+ [CLK_NAND0_0] = GATE(0x400, BIT(31)),
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+ [CLK_NAND0_1] = GATE(0x404, BIT(31)),
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+ [CLK_NAND1_0] = GATE(0x408, BIT(31)),
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+ [CLK_NAND1_1] = GATE(0x40c, BIT(31)),
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[CLK_SPI0] = GATE(0x430, BIT(31)),
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[CLK_SPI1] = GATE(0x434, BIT(31)),
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[CLK_SPI2] = GATE(0x438, BIT(31)),
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[CLK_SPI3] = GATE(0x43c, BIT(31)),
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[CLK_BUS_MMC] = GATE(0x580, BIT(8)),
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+ [CLK_BUS_NAND0] = GATE(0x580, BIT(12)),
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+ [CLK_BUS_NAND1] = GATE(0x580, BIT(13)),
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[CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
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[CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
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[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
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@@ -42,6 +48,8 @@ static const struct ccu_clk_gate a80_gat
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static const struct ccu_reset a80_resets[] = {
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[RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
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+ [RST_BUS_NAND0] = RESET(0x5a0, BIT(12)),
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+ [RST_BUS_NAND1] = RESET(0x5a0, BIT(13)),
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[RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
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[RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
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[RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
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--- a/drivers/clk/sunxi/clk_a83t.c
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+++ b/drivers/clk/sunxi/clk_a83t.c
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@@ -17,6 +17,7 @@ static struct ccu_clk_gate a83t_gates[]
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[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
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[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
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[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
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+ [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
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[CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
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[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
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[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
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@@ -36,6 +37,7 @@ static struct ccu_clk_gate a83t_gates[]
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[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
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[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
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+ [CLK_NAND] = GATE(0x080, BIT(31)),
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[CLK_SPI0] = GATE(0x0a0, BIT(31)),
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[CLK_SPI1] = GATE(0x0a4, BIT(31)),
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@@ -54,6 +56,7 @@ static struct ccu_reset a83t_resets[] =
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[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
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[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
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[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
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+ [RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
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[RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
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[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
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[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
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--- a/drivers/clk/sunxi/clk_h3.c
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+++ b/drivers/clk/sunxi/clk_h3.c
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@@ -19,6 +19,7 @@ static struct ccu_clk_gate h3_gates[] =
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[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
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[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
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[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
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+ [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
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[CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
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[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
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[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
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@@ -44,6 +45,7 @@ static struct ccu_clk_gate h3_gates[] =
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[CLK_BUS_EPHY] = GATE(0x070, BIT(0)),
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+ [CLK_NAND] = GATE(0x080, BIT(31)),
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[CLK_SPI0] = GATE(0x0a0, BIT(31)),
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[CLK_SPI1] = GATE(0x0a4, BIT(31)),
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@@ -66,6 +68,7 @@ static struct ccu_reset h3_resets[] = {
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[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
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[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
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[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
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+ [RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
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[RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
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[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
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[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
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--- a/drivers/clk/sunxi/clk_h6.c
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+++ b/drivers/clk/sunxi/clk_h6.c
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@@ -18,6 +18,10 @@ static struct ccu_clk_gate h6_gates[] =
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[CLK_APB1] = GATE_DUMMY,
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+ [CLK_NAND0] = GATE(0x810, BIT(31)),
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+ [CLK_NAND1] = GATE(0x814, BIT(31)),
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+ [CLK_BUS_NAND] = GATE(0x82c, BIT(0)),
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+
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[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
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[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
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[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
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@@ -58,6 +62,8 @@ static struct ccu_clk_gate h6_gates[] =
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};
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static struct ccu_reset h6_resets[] = {
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+ [RST_BUS_NAND] = RESET(0x82c, BIT(16)),
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+
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[RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
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[RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
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[RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
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--- a/drivers/clk/sunxi/clk_h616.c
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+++ b/drivers/clk/sunxi/clk_h616.c
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@@ -17,6 +17,10 @@ static struct ccu_clk_gate h616_gates[]
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[CLK_APB1] = GATE_DUMMY,
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+ [CLK_NAND0] = GATE(0x810, BIT(31)),
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+ [CLK_NAND1] = GATE(0x814, BIT(31)),
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+ [CLK_BUS_NAND] = GATE(0x82c, BIT(0)),
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+
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[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
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[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
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[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
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@@ -67,6 +71,8 @@ static struct ccu_clk_gate h616_gates[]
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};
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static struct ccu_reset h616_resets[] = {
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+ [RST_BUS_NAND] = RESET(0x82c, BIT(16)),
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+
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[RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
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[RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
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[RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
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--- a/drivers/clk/sunxi/clk_r40.c
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+++ b/drivers/clk/sunxi/clk_r40.c
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@@ -18,6 +18,7 @@ static struct ccu_clk_gate r40_gates[] =
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[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
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[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
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[CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
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+ [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
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[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
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[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
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[CLK_BUS_SPI2] = GATE(0x060, BIT(22)),
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@@ -48,6 +49,7 @@ static struct ccu_clk_gate r40_gates[] =
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[CLK_BUS_UART6] = GATE(0x06c, BIT(22)),
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[CLK_BUS_UART7] = GATE(0x06c, BIT(23)),
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+ [CLK_NAND] = GATE(0x080, BIT(31)),
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[CLK_SPI0] = GATE(0x0a0, BIT(31)),
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[CLK_SPI1] = GATE(0x0a4, BIT(31)),
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[CLK_SPI2] = GATE(0x0a8, BIT(31)),
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@@ -70,6 +72,7 @@ static struct ccu_reset r40_resets[] = {
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[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
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[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
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[RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
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+ [RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
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[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
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[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
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[RST_BUS_SPI2] = RESET(0x2c0, BIT(22)),
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