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428 lines
11 KiB
Diff
428 lines
11 KiB
Diff
From a69ac853def2f93194e244974f611477a1521a4a Mon Sep 17 00:00:00 2001
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From: Sean Wang <sean.wang@mediatek.com>
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Date: Thu, 28 Dec 2017 18:18:26 +0800
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Subject: [PATCH 216/224] arm64: dts: mt7622: add SoC and peripheral related
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device nodes
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Add watchdog, rtc, auxadc, cir, efuse, rng, uart[1-4], pwm, i2c[0-2],
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spi[0-1], btif and thermal related nodes.
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Cc: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
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Cc: Zhiyong Tao <zhiyong.tao@mediatek.com>
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Cc: Zhi Mao <zhi.mao@mediatek.com>
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Cc: Jun Gao <jun.gao@mediatek.com>
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Cc: Leilk Liu <leilk.liu@mediatek.com>
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Cc: Matthias Brugger <matthias.bgg@gmail.com>
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---
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arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 54 ++++++
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 264 +++++++++++++++++++++++++++
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2 files changed, 318 insertions(+)
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diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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index b3878656475c..ba6a79caca21 100644
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -235,6 +235,34 @@
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};
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};
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+&btif {
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+ status = "okay";
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+};
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+
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+&cir {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&irrx_pins>;
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+ status = "okay";
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+};
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+
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+&i2c1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c1_pins>;
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+ status = "okay";
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+};
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+
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+&i2c2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c2_pins>;
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+ status = "okay";
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+};
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+
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+&pwm {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pwm7_pins>;
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+ status = "okay";
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+};
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+
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&pwrap {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_bus_pins>;
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@@ -242,6 +270,32 @@
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status = "okay";
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};
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+&spi0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spic0_pins>;
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+ status = "okay";
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+};
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+
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+&spi1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spic1_pins>;
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+ status = "okay";
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+};
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+
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&uart0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_pins>;
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+ status = "okay";
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+};
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+
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+&uart2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart2_pins>;
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+ status = "okay";
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+};
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+
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+&watchdog {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&watchdog_pins>;
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status = "okay";
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};
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diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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index d8a17d10e2ff..448cd366995b 100644
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -11,6 +11,7 @@
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#include <dt-bindings/clock/mt7622-clk.h>
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#include <dt-bindings/power/mt7622-power.h>
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#include <dt-bindings/reset/mt7622-reset.h>
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+#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "mediatek,mt7622";
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@@ -74,6 +75,7 @@
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<&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table>;
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+ #cooling-cells = <2>;
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enable-method = "psci";
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clock-frequency = <1300000000>;
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};
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@@ -121,6 +123,58 @@
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};
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};
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+ thermal-zones {
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+ cpu_thermal: cpu-thermal {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&thermal 0>;
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+
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+ trips {
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+ cpu_passive: cpu-passive {
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+ temperature = <47000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ cpu_active: cpu-active {
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+ temperature = <67000>;
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+ hysteresis = <2000>;
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+ type = "active";
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+ };
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+
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+ cpu_hot: cpu-hot {
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+ temperature = <87000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+
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+ cpu-crit {
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+ temperature = <107000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map0 {
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+ trip = <&cpu_passive>;
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+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+
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+ map1 {
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+ trip = <&cpu_active>;
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+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+
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+ map2 {
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+ trip = <&cpu_hot>;
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+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+ };
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+ };
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+
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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@@ -176,6 +230,16 @@
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clock-names = "hif_sel";
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};
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+ cir: cir@10009000 {
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+ compatible = "mediatek,mt7622-cir";
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+ reg = <0 0x10009000 0 0x1000>;
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+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&infracfg CLK_INFRA_IRRX_PD>,
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+ <&topckgen CLK_TOP_AXI_SEL>;
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+ clock-names = "clk", "bus";
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+ status = "disabled";
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+ };
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+
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sysirq: interrupt-controller@10200620 {
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compatible = "mediatek,mt7622-sysirq",
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"mediatek,mt6577-sysirq";
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@@ -185,6 +249,18 @@
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reg = <0 0x10200620 0 0x20>;
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};
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+ efuse: efuse@10206000 {
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+ compatible = "mediatek,mt7622-efuse",
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+ "mediatek,efuse";
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+ reg = <0 0x10206000 0 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ thermal_calibration: calib@198 {
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+ reg = <0x198 0xc>;
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+ };
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+ };
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+
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apmixedsys: apmixedsys@10209000 {
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compatible = "mediatek,mt7622-apmixedsys",
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"syscon";
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@@ -199,6 +275,14 @@
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#clock-cells = <1>;
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};
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+ rng: rng@1020f000 {
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+ compatible = "mediatek,mt7622-rng",
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+ "mediatek,mt7623-rng";
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+ reg = <0 0x1020f000 0 0x1000>;
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+ clocks = <&infracfg CLK_INFRA_TRNG>;
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+ clock-names = "rng";
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+ };
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+
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pio: pinctrl@10211000 {
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compatible = "mediatek,mt7622-pinctrl";
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reg = <0 0x10211000 0 0x1000>;
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@@ -206,6 +290,21 @@
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#gpio-cells = <2>;
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};
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+ watchdog: watchdog@10212000 {
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+ compatible = "mediatek,mt7622-wdt",
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+ "mediatek,mt6589-wdt";
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+ reg = <0 0x10212000 0 0x800>;
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+ };
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+
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+ rtc: rtc@10212800 {
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+ compatible = "mediatek,mt7622-rtc",
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+ "mediatek,soc-rtc";
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+ reg = <0 0x10212800 0 0x200>;
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+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&topckgen CLK_TOP_RTC>;
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+ clock-names = "rtc";
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+ };
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+
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gic: interrupt-controller@10300000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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@@ -217,6 +316,14 @@
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<0 0x10360000 0 0x2000>;
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};
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+ auxadc: adc@11001000 {
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+ compatible = "mediatek,mt7622-auxadc";
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+ reg = <0 0x11001000 0 0x1000>;
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+ clocks = <&pericfg CLK_PERI_AUXADC_PD>;
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+ clock-names = "main";
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+ #io-channel-cells = <1>;
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+ };
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+
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uart0: serial@11002000 {
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compatible = "mediatek,mt7622-uart",
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"mediatek,mt6577-uart";
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@@ -228,6 +335,163 @@
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status = "disabled";
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};
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+ uart1: serial@11003000 {
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+ compatible = "mediatek,mt7622-uart",
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+ "mediatek,mt6577-uart";
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+ reg = <0 0x11003000 0 0x400>;
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+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&topckgen CLK_TOP_UART_SEL>,
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+ <&pericfg CLK_PERI_UART1_PD>;
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+ clock-names = "baud", "bus";
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+ status = "disabled";
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+ };
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+
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+ uart2: serial@11004000 {
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+ compatible = "mediatek,mt7622-uart",
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+ "mediatek,mt6577-uart";
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+ reg = <0 0x11004000 0 0x400>;
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+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&topckgen CLK_TOP_UART_SEL>,
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+ <&pericfg CLK_PERI_UART2_PD>;
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+ clock-names = "baud", "bus";
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+ status = "disabled";
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+ };
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+
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+ uart3: serial@11005000 {
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+ compatible = "mediatek,mt7622-uart",
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+ "mediatek,mt6577-uart";
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+ reg = <0 0x11005000 0 0x400>;
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+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&topckgen CLK_TOP_UART_SEL>,
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+ <&pericfg CLK_PERI_UART3_PD>;
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+ clock-names = "baud", "bus";
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+ status = "disabled";
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+ };
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+
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+ pwm: pwm@11006000 {
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+ compatible = "mediatek,mt7622-pwm";
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+ reg = <0 0x11006000 0 0x1000>;
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+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
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+ <&pericfg CLK_PERI_PWM_PD>,
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+ <&pericfg CLK_PERI_PWM1_PD>,
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+ <&pericfg CLK_PERI_PWM2_PD>,
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+ <&pericfg CLK_PERI_PWM3_PD>,
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+ <&pericfg CLK_PERI_PWM4_PD>,
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+ <&pericfg CLK_PERI_PWM5_PD>,
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+ <&pericfg CLK_PERI_PWM6_PD>;
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+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
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+ "pwm5", "pwm6";
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+ status = "disabled";
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+ };
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+
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+ i2c0: i2c@11007000 {
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+ compatible = "mediatek,mt7622-i2c";
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+ reg = <0 0x11007000 0 0x90>,
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+ <0 0x11000100 0 0x80>;
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+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
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+ clock-div = <16>;
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+ clocks = <&pericfg CLK_PERI_I2C0_PD>,
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+ <&pericfg CLK_PERI_AP_DMA_PD>;
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+ clock-names = "main", "dma";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c1: i2c@11008000 {
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+ compatible = "mediatek,mt7622-i2c";
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+ reg = <0 0x11008000 0 0x90>,
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+ <0 0x11000180 0 0x80>;
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+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
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+ clock-div = <16>;
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+ clocks = <&pericfg CLK_PERI_I2C1_PD>,
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+ <&pericfg CLK_PERI_AP_DMA_PD>;
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+ clock-names = "main", "dma";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c2: i2c@11009000 {
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+ compatible = "mediatek,mt7622-i2c";
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+ reg = <0 0x11009000 0 0x90>,
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+ <0 0x11000200 0 0x80>;
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+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
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+ clock-div = <16>;
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+ clocks = <&pericfg CLK_PERI_I2C2_PD>,
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+ <&pericfg CLK_PERI_AP_DMA_PD>;
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+ clock-names = "main", "dma";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi0: spi@1100a000 {
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+ compatible = "mediatek,mt7622-spi";
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+ reg = <0 0x1100a000 0 0x100>;
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+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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+ <&topckgen CLK_TOP_SPI0_SEL>,
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+ <&pericfg CLK_PERI_SPI0_PD>;
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+ clock-names = "parent-clk", "sel-clk", "spi-clk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ thermal: thermal@1100b000 {
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+ #thermal-sensor-cells = <1>;
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+ compatible = "mediatek,mt7622-thermal";
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+ reg = <0 0x1100b000 0 0x1000>;
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+ interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_THERM_PD>,
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+ <&pericfg CLK_PERI_AUXADC_PD>;
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+ clock-names = "therm", "auxadc";
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+ resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
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+ reset-names = "therm";
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+ mediatek,auxadc = <&auxadc>;
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+ mediatek,apmixedsys = <&apmixedsys>;
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+ nvmem-cells = <&thermal_calibration>;
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+ nvmem-cell-names = "calibration-data";
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+ };
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+
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+ btif: serial@1100c000 {
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+ compatible = "mediatek,mt7622-btif",
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+ "mediatek,mtk-btif";
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+ reg = <0 0x1100c000 0 0x1000>;
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+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_BTIF_PD>;
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+ clock-names = "main";
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+ reg-shift = <2>;
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+ reg-io-width = <4>;
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+ status = "disabled";
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+ };
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+
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+ spi1: spi@11016000 {
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+ compatible = "mediatek,mt7622-spi";
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+ reg = <0 0x11016000 0 0x100>;
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+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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+ <&topckgen CLK_TOP_SPI1_SEL>,
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+ <&pericfg CLK_PERI_SPI1_PD>;
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+ clock-names = "parent-clk", "sel-clk", "spi-clk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ uart4: serial@11019000 {
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+ compatible = "mediatek,mt7622-uart",
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+ "mediatek,mt6577-uart";
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+ reg = <0 0x11019000 0 0x400>;
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+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&topckgen CLK_TOP_UART_SEL>,
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+ <&pericfg CLK_PERI_UART4_PD>;
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+ clock-names = "baud", "bus";
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+ status = "disabled";
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+ };
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+
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ssusbsys: ssusbsys@1a000000 {
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compatible = "mediatek,mt7622-ssusbsys",
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"syscon";
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--
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2.11.0
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