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125 lines
4.3 KiB
Diff
125 lines
4.3 KiB
Diff
From 442c890727e0f585154662b0908fbe3a7986052a Mon Sep 17 00:00:00 2001
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From: Sean Wang <sean.wang@mediatek.com>
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Date: Wed, 18 Oct 2017 16:28:47 +0800
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Subject: [PATCH 121/224] soc: mediatek: pwrap: add common way for setup CS
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timing extenstion
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Multiple platforms would always use their own way handling CS timing
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extension on the bus which leads to a little bit code duplication.
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Therefore, the patch groups the similar logic to handle CS timing
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extension into the common function which allows the following SoCs
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have more reusability for configing CS timing.
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Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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---
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drivers/soc/mediatek/mtk-pmic-wrap.c | 59 ++++++++++++++++++++++--------------
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1 file changed, 37 insertions(+), 22 deletions(-)
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diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
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index 45c3e44d8f40..cbc3f0e82337 100644
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--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
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+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
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@@ -827,23 +827,44 @@ static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
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return 0;
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}
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-static int pwrap_mt8135_init_reg_clock(struct pmic_wrapper *wrp)
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+/*
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+ * pwrap_init_chip_select_ext is used to configure CS extension time for each
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+ * phase during data transactions on the pwrap bus.
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+ */
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+static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
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+ u8 hext_read, u8 lext_start,
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+ u8 lext_end)
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{
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- pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
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- pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
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- pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
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- pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
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- pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
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+ /*
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+ * After finishing a write and read transaction, extends CS high time
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+ * to be at least xT of BUS CLK as hext_write and hext_read specifies
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+ * respectively.
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+ */
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+ pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
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+ pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
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- return 0;
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+ /*
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+ * Extends CS low time after CSL and before CSH command to be at
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+ * least xT of BUS CLK as lext_start and lext_end specifies
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+ * respectively.
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+ */
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+ pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
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+ pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
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}
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-static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp)
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+static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
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{
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- pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
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- pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
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- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
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- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
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+ switch (wrp->master->type) {
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+ case PWRAP_MT8173:
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+ pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
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+ break;
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+ case PWRAP_MT8135:
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+ pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
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+ pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
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+ break;
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+ default:
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+ break;
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+ }
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return 0;
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}
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@@ -853,20 +874,14 @@ static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
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switch (wrp->slave->type) {
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case PMIC_MT6397:
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pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
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- pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE);
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- pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
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- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
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- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
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+ pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
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break;
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case PMIC_MT6323:
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pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
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pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
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0x8);
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- pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE);
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- pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
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- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
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- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
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+ pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
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break;
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default:
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break;
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@@ -1235,7 +1250,7 @@ static const struct pmic_wrapper_type pwrap_mt8135 = {
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.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
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.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
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.has_bridge = 1,
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- .init_reg_clock = pwrap_mt8135_init_reg_clock,
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+ .init_reg_clock = pwrap_common_init_reg_clock,
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.init_soc_specific = pwrap_mt8135_init_soc_specific,
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};
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@@ -1247,7 +1262,7 @@ static const struct pmic_wrapper_type pwrap_mt8173 = {
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.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
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.wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
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.has_bridge = 0,
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- .init_reg_clock = pwrap_mt8173_init_reg_clock,
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+ .init_reg_clock = pwrap_common_init_reg_clock,
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.init_soc_specific = pwrap_mt8173_init_soc_specific,
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};
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--
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2.11.0
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