openwrt/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

#include "mt7622.dtsi"
#include "mt6380.dtsi"

/ {
	model = "Xiaomi Redmi Router AX6S";
	compatible = "xiaomi,redmi-router-ax6s", "mediatek,mt7622";

	aliases {
		serial0 = &uart0;
		led-boot = &led_power_amber;
		led-failsafe = &led_power_amber;
		led-running = &led_power_blue;
		led-upgrade = &led_power_blue;
	};

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
	};

	memory {
		reg = <0 0x40000000 0 0x8000000>;
	};

	leds {
		compatible = "gpio-leds";

		led_power_blue: power_blue {
			label = "blue:power";
			gpios = <&pio 18 GPIO_ACTIVE_LOW>;
		};

		led_power_amber: power_amber {
			label = "amber:power";
			gpios = <&pio 17 GPIO_ACTIVE_LOW>;
		};

		led_net_blue: net_blue {
			label = "blue:net";
			gpios = <&pio 01 GPIO_ACTIVE_LOW>;
		};

		led_net_amber: net_amber {
			label = "amber:net";
			gpios = <&pio 16 GPIO_ACTIVE_LOW>;
		};

	};

	keys {
		compatible = "gpio-keys";

		reset {
			label = "reset";
			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};

		mesh {
			label = "mesh";
			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_9>;
			linux,input-type = <EV_SW>;
		};
	};
};

&cpu0 {
	proc-supply = <&mt6380_vcpu_reg>;
	sram-supply = <&mt6380_vm_reg>;
};

&cpu1 {
	proc-supply = <&mt6380_vcpu_reg>;
	sram-supply = <&mt6380_vm_reg>;
};

&pio {
	eth_pins: eth-pins {
		mux {
			function = "eth";
			groups = "mdc_mdio", "rgmii_via_gmac2";
		};
	};

	pcie0_pins: pcie0-pins {
		mux {
			function = "pcie";
			groups = "pcie0_pad_perst",
				 "pcie0_1_waken",
				 "pcie0_1_clkreq";
		};
	};

	pmic_bus_pins: pmic-bus-pins {
		mux {
			function = "pmic";
			groups = "pmic_bus";
		};
	};

	pwm7_pins: pwm1-2-pins {
		mux {
			function = "pwm";
			groups = "pwm_ch7_2";
		};
	};

	/* Serial NAND is shared pin with SPI-NOR */
	serial_nand_pins: serial-nand-pins {
		mux {
			function = "flash";
			groups = "snfi";
		};
	};

	uart0_pins: uart0-pins {
		mux {
			function = "uart";
			groups = "uart0_0_tx_rx" ;
		};
	};

	watchdog_pins: watchdog-pins {
		mux {
			function = "watchdog";
			groups = "watchdog";
		};
	};
};

&eth {
	pinctrl-names = "default";
	pinctrl-0 = <&eth_pins>;
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;

		phy-connection-type = "2500base-x";

		nvmem-cells = <&macaddr_factory_4>;
		nvmem-cell-names = "mac-address";
		mac-address-increment = <(-1)>;

		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
		};
	};

	mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		switch@0 {
			compatible = "mediatek,mt7531";
			reg = <0>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&pio>;
			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
			reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				wan: port@1 {
					reg = <1>;
					label = "wan";
				};

				port@2 {
					reg = <2>;
					label = "lan1";
				};

				port@3 {
					reg = <3>;
					label = "lan2";
				};

				port@4 {
					reg = <4>;
					label = "lan3";
				};

				port@6 {
					reg = <6>;
					ethernet = <&gmac0>;
					phy-mode = "2500base-x";

					fixed-link {
						speed = <2500>;
						full-duplex;
						pause;
					};
				};
			};
		};
	};
};

&bch {
	status = "okay";
};

&snfi {
	pinctrl-names = "default";
	pinctrl-0 = <&serial_nand_pins>;
	status = "okay";

	flash@0 {
		compatible = "spi-nand";
		reg = <0>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		nand-ecc-engine = <&snfi>;

		mediatek,bmt-v2;
		mediatek,bmt-table-size = <0x1000>;
		mediatek,bmt-remap-range = <0x0 0x6c0000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "Preloader";
				reg = <0x0 0x80000>;
				read-only;
			};

			partition@80000 {
				label = "ATF";
				reg = <0x80000 0x40000>;
				read-only;
			};

			partition@c0000 {
				label = "u-boot";
				reg = <0xc0000 0x80000>;
				read-only;
			};

			partition@140000 {
				label = "u-boot-env";
				reg = <0x140000 0x40000>;
			};

			partition@180000 {
				label = "bdata";
				reg = <0x180000 0x40000>;
			};

			factory: partition@1c0000 {
				label = "factory";
				reg = <0x1c0000 0x80000>;
				read-only;

				compatible = "nvmem-cells";
				#address-cells = <1>;
				#size-cells = <1>;

				macaddr_factory_4: macaddr@4 {
					reg = <0x4 0x6>;
				};
			};

			partition@240000 {
				label = "crash";
				reg = <0x240000 0x40000>;
				read-only;
			};

			partition@280000 {
				label = "crash_log";
				reg = <0x280000 0x40000>;
				read-only;
			};

			/* Shrunk and renamed from "firmware"
			 * as to not break luci size checks
			 */
			partition@2c0000 {
				label = "kernel";
				reg = <0x2c0000 0x400000>;
			};

			/* ubi partition is the result of squashing
			 * consecutive stock partitions:
			 * - firmware (partially)
			 * - firmware1
			 * - overlay
			 * - obr
			 */
			partition@6c0000 {
				label = "ubi";
				reg = <0x6C0000 0x6f00000>;
			};
		};
	};
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie0_pins>;
	status = "okay";
};

&slot0 {
	status = "okay";

	wifi@0,0 {
		compatible = "mediatek,mt76";
		reg = <0x0000 0 0 0 0>;
		mediatek,mtd-eeprom = <&factory 0x5000>;
		ieee80211-freq-limit = <5000000 6000000>;
		mediatek,disable-radar-background;
	};
};

&pwm {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm7_pins>;
	status = "okay";
};

&pwrap {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_bus_pins>;
	status = "okay";
};

&rtc {
	status = "disabled";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&watchdog {
	pinctrl-names = "default";
	pinctrl-0 = <&watchdog_pins>;
	status = "okay";
};

&wmac {
	status = "okay";

	mediatek,mtd-eeprom = <&factory 0x0>;
};