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cae808946a
Add patches and config for 4.14, refreshed from 4.9. Signed-off-by: Matti Laakso <matti.laakso@outlook.com>
50 lines
2.0 KiB
Diff
50 lines
2.0 KiB
Diff
From 3642843a06025ec333d7e92580cf52cb8db2a652 Mon Sep 17 00:00:00 2001
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From: Govindraj Raja <Govindraj.Raja@imgtec.com>
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Date: Fri, 8 Jan 2016 16:36:07 +0000
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Subject: clk: pistachio: Fix wrong SDHost card speed
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The SDHost currently clocks the card 4x slower than it
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should do, because there is fixed divide by 4 in the
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sdhost wrapper that is not present in the clock tree.
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To model this add a fixed divide by 4 clock node in
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the SDHost clock path.
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This will ensure the right clock frequency is selected when
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the mmc driver tries to configure frequency on card insert.
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Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
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---
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drivers/clk/pistachio/clk-pistachio.c | 3 ++-
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include/dt-bindings/clock/pistachio-clk.h | 1 +
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2 files changed, 3 insertions(+), 1 deletion(-)
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--- a/drivers/clk/pistachio/clk-pistachio.c
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+++ b/drivers/clk/pistachio/clk-pistachio.c
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@@ -44,7 +44,7 @@ static struct pistachio_gate pistachio_g
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GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",
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0x104, 22),
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GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
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- GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
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+ GATE(CLK_SD_HOST, "sd_host", "sd_host_div4", 0x104, 24),
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GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
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GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
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GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
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@@ -54,6 +54,7 @@ static struct pistachio_gate pistachio_g
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static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {
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FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4),
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FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8),
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+ FIXED_FACTOR(CLK_SDHOST_DIV4, "sd_host_div4", "sd_host_div", 4),
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};
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static struct pistachio_div pistachio_divs[] __initdata = {
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--- a/include/dt-bindings/clock/pistachio-clk.h
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+++ b/include/dt-bindings/clock/pistachio-clk.h
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@@ -21,6 +21,7 @@
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/* Fixed-factor clocks */
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#define CLK_WIFI_DIV4 16
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#define CLK_WIFI_DIV8 17
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+#define CLK_SDHOST_DIV4 18
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/* Gate clocks */
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#define CLK_MIPS 32
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