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On danube the USB0 registers are at 1e101000 similar to all other lantiq SoCs. On Danube and AR9 the USB core is connected to the AHB bus, hence we need to enable the AHB Bus as well. Signed-off-by: Mathias Kresin <dev@kresin.me>
26 lines
1.0 KiB
Diff
26 lines
1.0 KiB
Diff
From 11e84fdfad0331555ca889c4ac6a9d5f37ae83df Mon Sep 17 00:00:00 2001
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From: Mathias Kresin <dev@kresin.me>
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Date: Sat, 20 Jan 2018 14:38:40 +0100
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Subject: [PATCH] MIPS: lantiq: fix danube usb clock
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On danube the USB0 registers are at 1e101000 similar to all other lantiq
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SoCs.
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Fixes: dea54fbad332 ("phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module")
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Signed-off-by: Mathias Kresin <dev@kresin.me>
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---
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arch/mips/lantiq/xway/sysctrl.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -581,7 +581,7 @@ void __init ltq_soc_init(void)
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} else {
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clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
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ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
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- clkdev_add_pmu("1f203018.usb2-phy", "ctrl", 1, 0, PMU_USB0);
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+ clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
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clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
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clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
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clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
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