mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 09:12:39 +00:00
156f2df879
AP-DK01.1-C1 is QCA dev board with: - ipq4018 quad core ARM @716.8MHz, 2x2 dual (11n+11ac) radio - 256MB RAM - 32MB SPI flash - QCA8075 multiport ethernet phy (WAN port, 4x LAN ports) First installation via u-boot: sf probe sf erase 0x180000 0x1a00000 tftpboot 0x84000000 lede-ipq806x-AP-DK01.1-C1-squashfs-sysupgrade.bin sf write 0x84000000 0x180000 $filesize Further upgrades via sysupgrade. Changes: - add partitions - set memory size to 256MB - add reserved memory mapping - add correct compatible string - add image generation - extract pre-cal data from ART partition Compile and run tested. Wirespeed NAT can be achieved with spreading rx interrupts over different cores. Wifi speed is ~550Mbps @5GHz in open air. Note: AP-DK01.1-C1 is fully compatible with AP-DK01.2-C1, which has ipq4028 instead of ipq4018 on board. Changes since v2: - based on dts(i) rework/cleanup submitted: http://lists.infradead.org/pipermail/lede-dev/2017-October/009596.html - precise reserved memory mapping - more precise description - compatible string Signed-off-by: Roman Yeryomin <roman@advem.lv>
116 lines
2.0 KiB
Diff
116 lines
2.0 KiB
Diff
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
|
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
|
@@ -19,4 +19,112 @@
|
|
/ {
|
|
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
|
|
|
|
+ memory {
|
|
+ device_type = "memory";
|
|
+ reg = <0x80000000 0x10000000>;
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ #address-cells = <0x1>;
|
|
+ #size-cells = <0x1>;
|
|
+ ranges;
|
|
+
|
|
+ apps_bl@87000000 {
|
|
+ reg = <0x87000000 0x400000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ sbl@87400000 {
|
|
+ reg = <0x87400000 0x100000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ cnss_debug@87500000 {
|
|
+ reg = <0x87500000 0x600000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ cpu_context_dump@87b00000 {
|
|
+ reg = <0x87b00000 0x080000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ tz_apps@87b80000 {
|
|
+ reg = <0x87b80000 0x280000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ smem@87e00000 {
|
|
+ reg = <0x87e00000 0x080000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ tz@87e80000 {
|
|
+ reg = <0x87e80000 0x180000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&spi_0 {
|
|
+ mx25l25635f@0 {
|
|
+ compatible = "mx25l25635f", "jedec,spi-nor";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <24000000>;
|
|
+
|
|
+ SBL1@0 {
|
|
+ label = "SBL1";
|
|
+ reg = <0x0 0x40000>;
|
|
+ read-only;
|
|
+ };
|
|
+ MIBIB@40000 {
|
|
+ label = "MIBIB";
|
|
+ reg = <0x40000 0x20000>;
|
|
+ read-only;
|
|
+ };
|
|
+ QSEE@60000 {
|
|
+ label = "QSEE";
|
|
+ reg = <0x60000 0x60000>;
|
|
+ read-only;
|
|
+ };
|
|
+ CDT@c0000 {
|
|
+ label = "CDT";
|
|
+ reg = <0xc0000 0x10000>;
|
|
+ read-only;
|
|
+ };
|
|
+ DDRPARAMS@d0000 {
|
|
+ label = "DDRPARAMS";
|
|
+ reg = <0xd0000 0x10000>;
|
|
+ read-only;
|
|
+ };
|
|
+ APPSBLENV@e0000 {
|
|
+ label = "APPSBLENV";
|
|
+ reg = <0xe0000 0x10000>;
|
|
+ read-only;
|
|
+ };
|
|
+ APPSBL@f0000 {
|
|
+ label = "APPSBL";
|
|
+ reg = <0xf0000 0x80000>;
|
|
+ read-only;
|
|
+ };
|
|
+ ART@170000 {
|
|
+ label = "ART";
|
|
+ reg = <0x170000 0x10000>;
|
|
+ read-only;
|
|
+ };
|
|
+ kernel@180000 {
|
|
+ label = "kernel";
|
|
+ reg = <0x180000 0x400000>;
|
|
+ };
|
|
+ rootfs@580000 {
|
|
+ label = "rootfs";
|
|
+ reg = <0x580000 0x1600000>;
|
|
+ };
|
|
+ firmware@180000 {
|
|
+ label = "firmware";
|
|
+ reg = <0x180000 0x1a00000>;
|
|
+ };
|
|
+ };
|
|
};
|