mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 09:12:39 +00:00
103 lines
3.0 KiB
Diff
103 lines
3.0 KiB
Diff
--- a/arch/mips/ath79/irq.c
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+++ b/arch/mips/ath79/irq.c
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@@ -26,6 +26,9 @@
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#include "common.h"
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#include "machtypes.h"
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+static struct irq_chip ip2_chip;
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+static struct irq_chip ip3_chip;
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+
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static void ath79_misc_irq_handler(struct irq_desc *desc)
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{
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void __iomem *base = ath79_reset_base;
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@@ -145,8 +148,7 @@ static void ar934x_ip2_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip,
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- handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
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}
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@@ -174,7 +176,7 @@ static void qca953x_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
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}
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@@ -238,15 +240,13 @@ static void qca955x_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip,
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- handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
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for (i = ATH79_IP3_IRQ_BASE;
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i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip,
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- handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
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}
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@@ -331,13 +331,13 @@ static void qca956x_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
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for (i = ATH79_IP3_IRQ_BASE;
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i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
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@@ -463,8 +463,36 @@ IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar71
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#endif
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+static void ath79_ip2_disable(struct irq_data *data)
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+{
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+ disable_irq(ATH79_CPU_IRQ(2));
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+}
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+
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+static void ath79_ip2_enable(struct irq_data *data)
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+{
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+ enable_irq(ATH79_CPU_IRQ(2));
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+}
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+
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+static void ath79_ip3_disable(struct irq_data *data)
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+{
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+ disable_irq(ATH79_CPU_IRQ(3));
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+}
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+
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+static void ath79_ip3_enable(struct irq_data *data)
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+{
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+ enable_irq(ATH79_CPU_IRQ(3));
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+}
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+
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void __init arch_init_irq(void)
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{
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+ ip2_chip = dummy_irq_chip;
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+ ip2_chip.irq_disable = ath79_ip2_disable;
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+ ip2_chip.irq_enable = ath79_ip2_enable;
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+
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+ ip3_chip = dummy_irq_chip;
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+ ip3_chip.irq_disable = ath79_ip3_disable;
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+ ip3_chip.irq_enable = ath79_ip3_enable;
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+
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if (mips_machtype == ATH79_MACH_GENERIC_OF) {
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irqchip_init();
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return;
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