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Introduce EN7581 SoC support with currently rfb board supported. This is a new 64bit SoC from Airoha that is currently almost fully supported upstream with only the DTS missing. Setting source-only waiting for the full upstream support to be completed. Link: https://github.com/openwrt/openwrt/pull/16730 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
101 lines
3.2 KiB
Diff
101 lines
3.2 KiB
Diff
From dc869a40d73ee6e9f47d683690ae507e30e56044 Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Wed, 3 Jul 2024 18:12:42 +0200
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Subject: [PATCH 1/3] PCI: mediatek-gen3: Add mtk_gen3_pcie_pdata data
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structure
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Introduce mtk_gen3_pcie_pdata data structure in order to define
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multiple callbacks for each supported SoC.
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This is a preliminary patch to introduce EN7581 PCIe support.
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Link: https://lore.kernel.org/linux-pci/c193d1a87505d045e2e0ef33317bce17012ee095.1720022580.git.lorenzo@kernel.org
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
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Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Acked-by: Jianjun Wang <jianjun.wang@mediatek.com>
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---
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drivers/pci/controller/pcie-mediatek-gen3.c | 24 ++++++++++++++++++---
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1 file changed, 21 insertions(+), 3 deletions(-)
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--- a/drivers/pci/controller/pcie-mediatek-gen3.c
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+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
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@@ -100,6 +100,16 @@
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#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0)
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#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2)
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+struct mtk_gen3_pcie;
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+
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+/**
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+ * struct mtk_gen3_pcie_pdata - differentiate between host generations
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+ * @power_up: pcie power_up callback
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+ */
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+struct mtk_gen3_pcie_pdata {
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+ int (*power_up)(struct mtk_gen3_pcie *pcie);
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+};
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+
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/**
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* struct mtk_msi_set - MSI information for each set
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* @base: IO mapped register base
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@@ -131,6 +141,7 @@ struct mtk_msi_set {
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* @msi_sets: MSI sets information
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* @lock: lock protecting IRQ bit map
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* @msi_irq_in_use: bit map for assigned MSI IRQ
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+ * @soc: pointer to SoC-dependent operations
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*/
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struct mtk_gen3_pcie {
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struct device *dev;
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@@ -151,6 +162,8 @@ struct mtk_gen3_pcie {
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struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
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struct mutex lock;
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DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
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+
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+ const struct mtk_gen3_pcie_pdata *soc;
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};
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/* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
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@@ -904,7 +917,7 @@ static int mtk_pcie_setup(struct mtk_gen
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usleep_range(10, 20);
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/* Don't touch the hardware registers before power up */
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- err = mtk_pcie_power_up(pcie);
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+ err = pcie->soc->power_up(pcie);
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if (err)
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return err;
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@@ -939,6 +952,7 @@ static int mtk_pcie_probe(struct platfor
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pcie = pci_host_bridge_priv(host);
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pcie->dev = dev;
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+ pcie->soc = device_get_match_data(dev);
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platform_set_drvdata(pdev, pcie);
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err = mtk_pcie_setup(pcie);
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@@ -1054,7 +1068,7 @@ static int mtk_pcie_resume_noirq(struct
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struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
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int err;
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- err = mtk_pcie_power_up(pcie);
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+ err = pcie->soc->power_up(pcie);
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if (err)
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return err;
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@@ -1074,8 +1088,12 @@ static const struct dev_pm_ops mtk_pcie_
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mtk_pcie_resume_noirq)
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};
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+static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = {
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+ .power_up = mtk_pcie_power_up,
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+};
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+
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static const struct of_device_id mtk_pcie_of_match[] = {
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- { .compatible = "mediatek,mt8192-pcie" },
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+ { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
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{},
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};
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MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
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