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277 lines
7.3 KiB
C
277 lines
7.3 KiB
C
/*
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* originally drivers/net/tulip/tulip.h
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* Copyright 2000,2001 The Linux Kernel Team
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* Written/copyright 1994-2001 by Donald Becker.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __NET_TULIP_H__
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#define __NET_TULIP_H__
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/mii.h>
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#include <linux/crc32.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/netdevice.h>
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#include <linux/ethtool.h>
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#include <linux/timer.h>
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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/platform_device.h>
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#include <asm/unaligned.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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/* undefine, or define to various debugging levels (>4 == obscene levels) */
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#define TULIP_DEBUG 1
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#define VALID_INTR 0x0001a451
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#define ADM8668_WAN_IRQ 8
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#define ADM8668_LAN_IRQ 7
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#define ADM8668_WAN_MACADDR 0xb00205ac
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#define ADM8668_LAN_MACADDR 0xb0020404
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/* Offsets to the Command and Status Registers, "CSRs". All accesses
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must be longword instructions and quadword aligned. */
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enum tulip_offsets {
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CSR0 = 0,
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CSR1 = 0x08,
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CSR2 = 0x10,
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CSR3 = 0x18,
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CSR4 = 0x20,
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CSR5 = 0x28,
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CSR6 = 0x30,
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CSR7 = 0x38,
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CSR8 = 0x40,
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CSR9 = 0x48,
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CSR10 = 0x50,
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CSR11 = 0x58,
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CSR12 = 0x60,
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CSR13 = 0x68,
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CSR14 = 0x70,
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CSR15 = 0x78,
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CSR18 = 0x88,
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CSR19 = 0x8c,
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CSR20 = 0x90,
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CSR27 = 0xAC,
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CSR28 = 0xB0,
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};
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#define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
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/* The bits in the CSR5 status registers, mostly interrupt sources. */
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enum status_bits {
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TimerInt = 0x800,
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SystemError = 0x2000,
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TPLnkFail = 0x1000,
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TPLnkPass = 0x10,
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NormalIntr = 0x10000,
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AbnormalIntr = 0x8000,
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RxJabber = 0x200,
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RxDied = 0x100,
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RxNoBuf = 0x80,
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RxIntr = 0x40,
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TxFIFOUnderflow = 0x20,
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RxErrIntr = 0x10,
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TxJabber = 0x08,
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TxNoBuf = 0x04,
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TxDied = 0x02,
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TxIntr = 0x01,
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};
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/* bit mask for CSR5 TX/RX process state */
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#define CSR5_TS 0x00700000
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#define CSR5_RS 0x000e0000
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enum tulip_mode_bits {
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TxThreshold = (1 << 22),
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FullDuplex = (1 << 9),
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TxOn = 0x2000,
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AcceptBroadcast = 0x0100,
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AcceptAllMulticast = 0x0080,
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AcceptAllPhys = 0x0040,
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AcceptRunt = 0x0008,
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RxOn = 0x0002,
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RxTx = (TxOn | RxOn),
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};
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/* The Tulip Rx and Tx buffer descriptors. */
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struct tulip_rx_desc {
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__le32 status;
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__le32 length;
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__le32 buffer1;
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__le32 buffer2;
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};
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struct tulip_tx_desc {
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__le32 status;
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__le32 length;
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__le32 buffer1;
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__le32 buffer2; /* We use only buffer 1. */
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};
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enum desc_status_bits {
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DescOwned = 0x80000000,
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DescWholePkt = 0x60000000,
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DescEndPkt = 0x40000000,
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DescStartPkt = 0x20000000,
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DescEndRing = 0x02000000,
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DescUseLink = 0x01000000,
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/*
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* Error summary flag is logical or of 'CRC Error', 'Collision Seen',
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* 'Frame Too Long', 'Runt' and 'Descriptor Error' flags generated
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* within tulip chip.
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*/
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RxDescErrorSummary = 0x8000,
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RxDescCRCError = 0x0002,
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RxDescCollisionSeen = 0x0040,
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/*
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* 'Frame Too Long' flag is set if packet length including CRC exceeds
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* 1518. However, a full sized VLAN tagged frame is 1522 bytes
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* including CRC.
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*
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* The tulip chip does not block oversized frames, and if this flag is
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* set on a receive descriptor it does not indicate the frame has been
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* truncated. The receive descriptor also includes the actual length.
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* Therefore we can safety ignore this flag and check the length
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* ourselves.
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*/
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RxDescFrameTooLong = 0x0080,
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RxDescRunt = 0x0800,
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RxDescDescErr = 0x4000,
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RxWholePkt = 0x00000300,
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/*
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* Top three bits of 14 bit frame length (status bits 27-29) should
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* never be set as that would make frame over 2047 bytes. The Receive
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* Watchdog flag (bit 4) may indicate the length is over 2048 and the
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* length field is invalid.
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*/
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RxLengthOver2047 = 0x38000010
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};
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/* Keep the ring sizes a power of two for efficiency.
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Making the Tx ring too large decreases the effectiveness of channel
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bonding and packet priority.
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There are no ill effects from too-large receive rings. */
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#define TX_RING_SIZE 32
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#define RX_RING_SIZE 128
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/* The receiver on the DC21143 rev 65 can fail to close the last
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* receive descriptor in certain circumstances (see errata) when
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* using MWI. This can only occur if the receive buffer ends on
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* a cache line boundary, so the "+ 4" below ensures it doesn't.
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*/
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#define PKT_BUF_SZ (1536 + 4) /* Size of each temporary Rx buffer. */
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/* Ring-wrap flag in length field, use for last ring entry.
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0x01000000 means chain on buffer2 address,
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0x02000000 means use the ring start address in CSR2/3.
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Note: Some work-alike chips do not function correctly in chained mode.
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The ASIX chip works only in chained mode.
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Thus we indicates ring mode, but always write the 'next' field for
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chained mode as well.
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*/
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#define DESC_RING_WRAP 0x02000000
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struct ring_info {
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struct sk_buff *skb;
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dma_addr_t mapping;
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};
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struct tulip_private {
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struct tulip_rx_desc *rx_ring;
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struct tulip_tx_desc *tx_ring;
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dma_addr_t rx_ring_dma;
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dma_addr_t tx_ring_dma;
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/* The saved address of a sent-in-place packet/buffer, for skfree(). */
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struct ring_info tx_buffers[TX_RING_SIZE];
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/* The addresses of receive-in-place skbuffs. */
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struct ring_info rx_buffers[RX_RING_SIZE];
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struct napi_struct napi;
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struct net_device_stats stats;
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struct timer_list oom_timer; /* Out of memory timer. */
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u32 mc_filter[2];
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spinlock_t lock;
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unsigned int cur_rx, cur_tx; /* The next free ring entry */
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unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
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unsigned int csr0; /* CSR0 setting. */
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unsigned int csr6; /* Current CSR6 control settings. */
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void (*link_change) (struct net_device * dev, int csr5);
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struct platform_device *pdev;
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unsigned long nir;
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void __iomem *base_addr;
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int pad0; /* Used for 8-byte alignment */
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struct net_device *dev;
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};
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/* interrupt.c */
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irqreturn_t tulip_interrupt(int irq, void *dev_instance);
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int tulip_refill_rx(struct net_device *dev);
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int tulip_poll(struct napi_struct *napi, int budget);
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/* tulip_core.c */
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extern int tulip_debug;
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void oom_timer(unsigned long data);
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static inline void tulip_start_rxtx(struct tulip_private *tp)
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{
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void __iomem *ioaddr = tp->base_addr;
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iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
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barrier();
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(void) ioread32(ioaddr + CSR6); /* mmio sync */
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}
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static inline void tulip_stop_rxtx(struct tulip_private *tp)
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{
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void __iomem *ioaddr = tp->base_addr;
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u32 csr6 = ioread32(ioaddr + CSR6);
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if (csr6 & RxTx) {
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unsigned i=1300/10;
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iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
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barrier();
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/* wait until in-flight frame completes.
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* Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
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* Typically expect this loop to end in < 50 us on 100BT.
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*/
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while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
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udelay(10);
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if (!i)
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printk(KERN_DEBUG "fixme: tulip_stop_rxtx() failed"
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" (CSR5 0x%x CSR6 0x%x)\n",
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ioread32(ioaddr + CSR5),
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ioread32(ioaddr + CSR6));
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}
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}
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static inline void tulip_restart_rxtx(struct tulip_private *tp)
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{
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tulip_stop_rxtx(tp);
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udelay(5);
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tulip_start_rxtx(tp);
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}
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static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr)
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{
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/* Stop and restart the chip's Tx processes. */
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tulip_restart_rxtx(tp);
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/* Trigger an immediate transmit demand. */
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iowrite32(0, ioaddr + CSR1);
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tp->stats.tx_errors++;
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}
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#endif /* __NET_TULIP_H__ */
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