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dc7efaefb5
Hardware Highlights:
This patch adds support for Western Digital MyBook Live Series:
CPU: AMCC PowerPC UNKNOWN (PVR=12c41c83) at 800 MHz (PLB=200, OPB=100, EBC=100 MHz)
32 kB I-Cache 32 kB D-Cache, 256 kB L2-Cache, 32 kB OnChip Memory
Board: Apollo-3G - APM82181 Board, 1*SATA
DRAM: 256 MB (2x NT5TU64M16GG-AC)
FLASH: 512 kB (SST 39VF040)
Ethernet: 1xRGMII - 1 Gbit - Broadcom PHY BCM54610
WARNING: The serial port needs a TTL/RS-232 v3.3 level converter!
The MyBook Live Duo additionally features a 1x USB 2.0 host port
and can support a second hard-drive.
This target produces two images for a target.
1. ext4 image
The extracted/raw image can be directly installed on
the internal HDD via "dd if=img.ext4 of=/dev/sdX".
This can either be done in place with the stock MyBook Live
firmware via ssh. Or by removing the HDD and writing the image
with a different PC.
The the compressed images are useful for sysupgrade.
2. recovery.tar image for TFTP and Serial.
extract the recovery.tar to a TFTP server directory.
On the MyBook Live (Duo) serial port - Hit Enter during u-boot and insert:
# setenv serverip 192.168.1.254; setenv ipaddr 192.168.1.1; run net_self
Where 192.168.1.254 is your TFTP server.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
490 lines
11 KiB
Plaintext
490 lines
11 KiB
Plaintext
/*
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* Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
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* (c) Copyright 2010 Western Digital Technologies, Inc. All Rights Reserved.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/ {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "amcc,apollo3g";
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dcr-parent = <&{/cpus/cpu@0}>;
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aliases {
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ethernet0 = &EMAC0;
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serial0 = &UART0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,apm82181";
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reg = <0x00000000>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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timebase-frequency = <0>; /* Filled in by U-Boot */
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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next-level-cache = <&L2C0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
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};
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UIC0: interrupt-controller0 {
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compatible = "ibm,uic-460ex","ibm,uic";
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interrupt-controller;
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cell-index = <0>;
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dcr-reg = <0x0c0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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UIC1: interrupt-controller1 {
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compatible = "ibm,uic-460ex","ibm,uic";
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interrupt-controller;
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cell-index = <1>;
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dcr-reg = <0x0d0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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UIC2: interrupt-controller2 {
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compatible = "ibm,uic-460ex","ibm,uic";
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interrupt-controller;
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cell-index = <2>;
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dcr-reg = <0x0e0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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UIC3: interrupt-controller3 {
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compatible = "ibm,uic-460ex","ibm,uic";
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interrupt-controller;
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cell-index = <3>;
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dcr-reg = <0x0f0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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OCM1: ocm@400040000 {
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compatible = "ibm,ocm";
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status = "okay";
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cell-index = <1>;
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/* configured in U-Boot */
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reg = <4 0x00040000 0x8000>; /* 32K */
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};
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SDR0: sdr {
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compatible = "ibm,sdr-460ex";
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dcr-reg = <0x00e 0x002>;
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};
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CPR0: cpr {
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compatible = "ibm,cpr-460ex";
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dcr-reg = <0x00c 0x002>;
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};
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CPM0: cpm {
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compatible = "ibm,cpm";
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dcr-access-method = "native";
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dcr-reg = <0x160 0x003>;
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unused-units = <0x00000100>;
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idle-doze = <0x02000000>;
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standby = <0xfeff791d>;
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};
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L2C0: l2c {
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compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
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dcr-reg = <0x020 0x008
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0x030 0x008>;
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cache-line-size = <32>;
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cache-size = <262144>;
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interrupt-parent = <&UIC1>;
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interrupts = <11 1>;
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};
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plb {
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compatible = "ibm,plb-460ex", "ibm,plb4";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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clock-frequency = <0>; /* Filled in by U-Boot */
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SDRAM0: sdram {
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compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
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dcr-reg = <0x010 0x002>;
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};
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CRYPTO: crypto@180000 {
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compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
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reg = <4 0x00180000 0x80400>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x1d 0x4>;
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};
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PKA: pka@114000 {
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device_type = "pka";
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compatible = "ppc4xx-pka", "amcc,ppc4xx-pka";
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reg = <0 0x00114000 0x4000>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x14 0x2>;
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};
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HWRNG: trng@110000 {
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compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
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reg = <4 0x00110000 0x50>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
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descriptor-memory = "ocm";
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dcr-reg = <0x180 0x062>;
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num-tx-chans = <1>;
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num-rx-chans = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-parent = <&UIC2>;
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interrupts = < /*TXEOB*/ 0x6 0x4
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/*RXEOB*/ 0x7 0x4
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/*SERR*/ 0x3 0x4
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/*TXDE*/ 0x4 0x4
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/*RXDE*/ 0x5 0x4
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/*TX0 COAL*/ 0x8 0x2
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/*TX1 COAL 0x9 0x2*/
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/*RX0 COAL*/ 0xc 0x2
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/*RX1 COAL 0xd 0x2*/ >;
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};
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AHBDMA: dma@bffd0800 {
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compatible = "snps,dma-spear1340";
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reg = <4 0xbffd0800 0x400>;
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interrupt-parent = <&UIC0>;
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interrupts = <25 4>;
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#dma-cells = <3>;
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/* use autoconfiguration for the dma setup */
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};
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SATA0: sata@bffd1000 {
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compatible = "amcc,sata-460ex";
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reg = <4 0xbffd1000 0x800>;
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interrupt-parent = <&UIC0>;
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interrupts = <26 4>;
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dmas = <&AHBDMA 0 0 1>;
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dma-names = "sata-dma";
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};
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SATA1: sata@bffd1800 {
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compatible = "amcc,sata-460ex";
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reg = <4 0xbffd1800 0x800>;
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interrupt-parent = <&UIC0>;
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interrupts = <27 4>;
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dmas = <&AHBDMA 1 0 2>;
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dma-names = "sata-dma";
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};
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USBOTG0: usbotg@bff80000 {
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compatible = "snps,dwc2";
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reg = <4 0xbff80000 0x10000>;
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interrupt-parent = <&USBOTG0>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </* USB-OTG */ 0 &UIC2 0x1c 4
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/* HIGH-POWER */ 1 &UIC1 0x1a 8
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/* DMA */ 2 &UIC0 0xc 4>;
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dr_mode = "host";
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};
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POB0: opb {
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compatible = "ibm,opb-460ex", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xb0000000 0x4 0xb0000000 0x50000000>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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EBC0: ebc {
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compatible = "ibm,ebc-460ex", "ibm,ebc";
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dcr-reg = <0x012 0x002>;
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#address-cells = <2>;
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#size-cells = <1>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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interrupts = <0x6 0x4>;
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interrupt-parent = <&UIC1>;
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/* ranges property are supplied by U-Boot */
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ranges = <0x0 0x0 0xfff80000 0x00080000
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0x1 0x0 0x00000000 0x00000000
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0x2 0x0 0x00000000 0x00000000>;
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/* Define device tree for Apollo3g NAS NOR flash
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* The NOR doesn't work when "enable-button" GPIO
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* is asserted.
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*/
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nor_flash@0,0 {
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compatible = "amd,s29gl512n", "jedec-probe", "cfi-flash", "mtd-rom";
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bank-width = <1>;
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reg = <0x00000000 0x00000000 0x00080000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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/* Part of bootrom - Don't use it without a jump */
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label = "free";
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reg = <0x00000000 0x0001e000>;
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};
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partition@1 {
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label = "env";
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reg = <0x0001e000 0x00002000>;
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};
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partition@2 {
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label = "uboot";
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reg = <0x00020000 0x00050000>;
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};
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};
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ndfc@1,0 {
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compatible = "ibm,ndfc";
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reg = <0x00000001 0x00000000 0x00002000>;
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ccr = <0x00001000>;
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bank-settings = <0x80002222>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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nand {
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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};
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gpio0: gpio0@e0000000 {
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compatible = "wd,mbl-gpio", "ti,74273";
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reg-names = "dat";
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reg = <0xe0000000 0x1>;
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#gpio-cells = <2>;
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gpio-controller;
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enable-phy {
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/* toggle to reset EMAC PHY */
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gpio-hog;
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line-name = "enable EMAC PHY";
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gpios = <0 1>;
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output-low;
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};
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enable-button {
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/* Defined in u-boot as: NOT_NOR
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* "enables features other than NOR
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* specifically, the buffer at CS2"
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* (button).
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*
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* Note: This option is disabled as
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* it prevents the system from being
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* rebooted successfully.
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*/
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gpio-hog;
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line-name = "Enable Reset Button, disable NOR";
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gpios = <1 0>;
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output-low;
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};
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enable-usb {
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gpio-hog;
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line-name = "Power USB Core";
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gpios = <2 1>;
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output-low;
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};
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enable-port1 {
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gpio-hog;
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line-name = "Power Drive Port 1";
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gpios = <3 1>;
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output-low;
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};
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enable-port0 {
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gpio-hog;
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line-name = "Power Drive Port 0";
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gpios = <7 1>;
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output-low;
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};
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};
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gpio1: gpio1@e0100000 {
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compatible = "wd,mbl-gpio", "ti,74244";
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reg-names = "dat";
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reg = <0xe0100000 0x1>;
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#gpio-cells = <2>;
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gpio-controller;
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no-output;
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};
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UART0: serial@ef600300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xef600300 0x00000008>;
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virtual-reg = <0xef600300>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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current-speed = <0>; /* Filled in by U-Boot */
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interrupt-parent = <&UIC1>;
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interrupts = <0x1 0x4>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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power-red {
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label = "mbl:red:power";
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gpios = <&gpio0 4 0>;
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linux,default-trigger = "panic";
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};
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power-green {
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label = "mbl:green:power";
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gpios = <&gpio0 5 0>;
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linux,default-trigger = "default-on";
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};
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power-blue {
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label = "mbl:blue:power";
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gpios = <&gpio0 6 0>;
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linux,default-trigger = "cpu0";
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};
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};
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gpio_keys_polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <60>; /* 3 * 20 = 60ms */
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autorepeat;
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button@1 {
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label = "Reset button";
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linux,code = <0x198>; /* KEY_RESTART */
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gpios = <&gpio1 2 1>;
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};
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};
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RGMII0: emac-rgmii@ef601500 {
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compatible = "ibm,rgmii-405ex", "ibm,rgmii";
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reg = <0xef601500 0x00000008>;
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has-mdio;
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};
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TAH0: emac-tah@ef601350 {
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compatible = "ibm,tah-460ex", "ibm,tah";
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reg = <0xef601350 0x00000030>;
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};
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EMAC0: ethernet@ef600c00 {
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device_type = "network";
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compatible = "ibm,emac-405ex", "ibm,emac4sync";
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interrupt-parent = <&EMAC0>;
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interrupts = <0x0 0x1>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
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/*Wake*/ 0x1 &UIC2 0x14 0x4>;
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reg = <0xef600c00 0x000000c4>;
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local-mac-address = [000000000000]; /* Filled in by U-Boot */
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mal-device = <&MAL0>;
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mal-tx-channel = <0>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <9000>;
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rx-fifo-size = <16384>;
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tx-fifo-size = <2048>;
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phy-mode = "rgmii";
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phy-map = <0x00000000>;
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rgmii-device = <&RGMII0>;
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rgmii-channel = <0>;
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tah-device = <&TAH0>;
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tah-channel = <0>;
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has-inverted-stacr-oc;
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has-new-stacr-staopc;
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};
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};
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ADMA: adma {
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compatible = "amcc,apm82181-adma";
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device_type = "dma";
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#address-cells = <2>;
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#size-cells = <1>;
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dma-4channel@1 {
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compatible = "amcc,apm82181-dma-4channel";
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cell-index = <1>;
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label = "plb_dma1";
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interrupt-parent = <&UIC0>;
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interrupts = <0xd 0x4>;
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pool_size = <0x4000>;
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dcr-reg = <0x208 0x20f>;
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};
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dma-4channel@2 {
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compatible = "amcc,apm82181-dma-4channel";
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cell-index = <2>;
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label = "plb_dma2";
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interrupt-parent = <&UIC0>;
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interrupts = <0xe 0x4>;
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pool_size = <0x4000>;
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dcr-reg = <0x210 0x217>;
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};
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dma-4channel@3 {
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compatible = "amcc,apm82181-dma-4channel";
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cell-index = <3>;
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label = "plb_dma3";
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interrupt-parent = <&UIC0>;
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interrupts = <0xf 0x4>;
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pool_size = <0x4000>;
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dcr-reg = <0x218 0x21f>;
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};
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};
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DMA: plb_dma@400300200 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "amcc,dma";
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cell-index = <0>;
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reg = <4 00300200 200>;
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dcr-reg = <0x100 0x13f>;
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interrupt-parent = <&UIC0>;
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interrupts = <0>;
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interrupt-map = < /* chan0 */ 0 &UIC0 12 4>;
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dma-4channel@0{
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compatible = "amcc,dma-4channel";
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cell-index = <0>;
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label = "channel0";
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reg = <0x100 0x107>;
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};
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};
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};
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};
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