mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 22:47:56 +00:00
15a14cf166
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LEDE/OPENWRT will auto strip executable program file while make. So we need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network fiemware be destroyed, then run make to build ls1012ardb firmware. The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message. This issue have noticed the IP owner for investigate, hope he can solve it earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4" bootargs. Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
42 lines
1.2 KiB
Diff
42 lines
1.2 KiB
Diff
From e892dea7229d56b75c46a76b9039f9e179584a91 Mon Sep 17 00:00:00 2001
|
|
From: Yunhui Cui <B56489@freescale.com>
|
|
Date: Mon, 1 Feb 2016 18:48:49 +0800
|
|
Subject: [PATCH 100/113] mtd:spi_nor: Disable Micron flash HW protection
|
|
|
|
For Micron family ,The status register write enable/disable bit,
|
|
provides hardware data protection for the device.
|
|
When the enable/disable bit is set to 1, the status register
|
|
nonvolatile bits become read-only and the WRITE STATUS REGISTER
|
|
operation will not execute.
|
|
|
|
Signed-off-by: Yunhui Cui <B56489@freescale.com>
|
|
---
|
|
drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
|
|
1 file changed, 9 insertions(+)
|
|
|
|
--- a/drivers/mtd/spi-nor/spi-nor.c
|
|
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
|
@@ -39,6 +39,7 @@
|
|
|
|
#define SPI_NOR_MAX_ID_LEN 6
|
|
#define SPI_NOR_MAX_ADDR_WIDTH 4
|
|
+#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
|
|
|
|
struct flash_info {
|
|
char *name;
|
|
@@ -1237,6 +1238,14 @@ int spi_nor_scan(struct spi_nor *nor, co
|
|
if (ret)
|
|
return ret;
|
|
|
|
+ if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
|
|
+ ret = read_sr(nor);
|
|
+ ret &= SPI_NOR_MICRON_WRITE_ENABLE;
|
|
+
|
|
+ write_enable(nor);
|
|
+ write_sr(nor, ret);
|
|
+ }
|
|
+
|
|
if (!mtd->name)
|
|
mtd->name = dev_name(dev);
|
|
mtd->priv = nor;
|