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9baca41064
Rearrange all voltage triplets for "opp_table0" to match the
specifications. "opp-microvolt" and "opp-microvolt-<name>" triplets
are in order of <target min max>, and NOT <min target max>.
Previously, the CPU would *always* spend its time at the "minimum"
voltage, ignoring the actual intended target. This is a regression
from previous behavior.
On an NBG6817 with a Qualcomm CPU of PVS bin #2...
(see &opp_table0 -> opp-1725000000 -> opp-microvolt-speed0-pvs2-v0)
* Before:
/usr/bin/tail -n +1 /sys/kernel/debug/opp/cpu0/opp\:1725000000/supply-0/u_volt_*
==> /sys/kernel/debug/opp/cpu0/opp:1725000000/supply-0/u_volt_max <==
1260000
==> /sys/kernel/debug/opp/cpu0/opp:1725000000/supply-0/u_volt_min <==
1200000
==> /sys/kernel/debug/opp/cpu0/opp:1725000000/supply-0/u_volt_target <==
1140000
* After:
/usr/bin/tail -n +1 /sys/kernel/debug/opp/cpu0/opp\:1725000000/supply-0/u_volt_*
==> /sys/kernel/debug/opp/cpu0/opp:1725000000/supply-0/u_volt_max <==
1260000
==> /sys/kernel/debug/opp/cpu0/opp:1725000000/supply-0/u_volt_min <==
1140000
==> /sys/kernel/debug/opp/cpu0/opp:1725000000/supply-0/u_volt_target <==
1200000
To check voltages and frequencies at run time, use...
/bin/cat /sys/kernel/debug/regulator/regulator_summary &&
/bin/cat /sys/kernel/debug/clk/clk_summary | grep "hfpll"
See
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/Documentation/devicetree/bindings/opp/opp.txt?h=v5.4.142#n91
Fixes: 1e25423be8 ("ipq806x: refresh dtsi patches")
Signed-off-by: Shane Synan <digitalcircuit36939@gmail.com>
Reviewed-by: Ansuel Smith <ansuelsmth@gmail.com>
[commit message style cleanup, another kernel refresh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
45 lines
1.2 KiB
Diff
45 lines
1.2 KiB
Diff
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -750,6 +750,41 @@
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reg = <0x12100000 0x10000>;
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};
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+ gsbi1: gsbi@12440000 {
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+ compatible = "qcom,gsbi-v1.0.0";
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+ cell-index = <1>;
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+ reg = <0x12440000 0x100>;
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+ clocks = <&gcc GSBI1_H_CLK>;
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+ clock-names = "iface";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ status = "disabled";
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+
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+ syscon-tcsr = <&tcsr>;
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+
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+ gsbi1_serial: serial@12450000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x12450000 0x100>,
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+ <0x12400000 0x03>;
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+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+
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+ gsbi1_i2c: i2c@12460000 {
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+ compatible = "qcom,i2c-qup-v1.1.1";
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+ reg = <0x12460000 0x1000>;
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+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
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+ clock-names = "core", "iface";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+
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gsbi2: gsbi@12480000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <2>;
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