mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 23:12:32 +00:00
110 lines
3.4 KiB
Diff
110 lines
3.4 KiB
Diff
From f844ea32cba0c4030594a0f590725477a5751f32 Mon Sep 17 00:00:00 2001
|
|
From: Annaliese McDermond <nh6z@nh6z.net>
|
|
Date: Thu, 21 Mar 2019 17:58:49 -0700
|
|
Subject: [PATCH 403/806] ASoC: tlv320aic32x4: Control clock gating with CCF
|
|
|
|
commit d25970b5fd51e9fcf0afbe190908ea4049454da4 upstream.
|
|
|
|
Control the clock gating to the various clock components to use
|
|
the CCF. This allows us to prepare_enalbe only 3 clocks and the
|
|
relationships assigned to them will cause upstream clockss to
|
|
enable automatically. Additionally we can do this in a single
|
|
call to the CCF.
|
|
|
|
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
|
|
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
---
|
|
sound/soc/codecs/tlv320aic32x4.c | 67 +++++++-------------------------
|
|
1 file changed, 13 insertions(+), 54 deletions(-)
|
|
|
|
--- a/sound/soc/codecs/tlv320aic32x4.c
|
|
+++ b/sound/soc/codecs/tlv320aic32x4.c
|
|
@@ -836,41 +836,25 @@ static int aic32x4_mute(struct snd_soc_d
|
|
static int aic32x4_set_bias_level(struct snd_soc_component *component,
|
|
enum snd_soc_bias_level level)
|
|
{
|
|
- struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
|
|
int ret;
|
|
|
|
+ struct clk_bulk_data clocks[] = {
|
|
+ { .id = "madc" },
|
|
+ { .id = "mdac" },
|
|
+ { .id = "bdiv" },
|
|
+ };
|
|
+
|
|
+ ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
switch (level) {
|
|
case SND_SOC_BIAS_ON:
|
|
- /* Switch on master clock */
|
|
- ret = clk_prepare_enable(aic32x4->mclk);
|
|
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
|
|
if (ret) {
|
|
- dev_err(component->dev, "Failed to enable master clock\n");
|
|
+ dev_err(component->dev, "Failed to enable clocks\n");
|
|
return ret;
|
|
}
|
|
-
|
|
- /* Switch on PLL */
|
|
- snd_soc_component_update_bits(component, AIC32X4_PLLPR,
|
|
- AIC32X4_PLLEN, AIC32X4_PLLEN);
|
|
-
|
|
- /* Switch on NDAC Divider */
|
|
- snd_soc_component_update_bits(component, AIC32X4_NDAC,
|
|
- AIC32X4_NDACEN, AIC32X4_NDACEN);
|
|
-
|
|
- /* Switch on MDAC Divider */
|
|
- snd_soc_component_update_bits(component, AIC32X4_MDAC,
|
|
- AIC32X4_MDACEN, AIC32X4_MDACEN);
|
|
-
|
|
- /* Switch on NADC Divider */
|
|
- snd_soc_component_update_bits(component, AIC32X4_NADC,
|
|
- AIC32X4_NADCEN, AIC32X4_NADCEN);
|
|
-
|
|
- /* Switch on MADC Divider */
|
|
- snd_soc_component_update_bits(component, AIC32X4_MADC,
|
|
- AIC32X4_MADCEN, AIC32X4_MADCEN);
|
|
-
|
|
- /* Switch on BCLK_N Divider */
|
|
- snd_soc_component_update_bits(component, AIC32X4_BCLKN,
|
|
- AIC32X4_BCLKEN, AIC32X4_BCLKEN);
|
|
break;
|
|
case SND_SOC_BIAS_PREPARE:
|
|
break;
|
|
@@ -879,32 +863,7 @@ static int aic32x4_set_bias_level(struct
|
|
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
|
|
break;
|
|
|
|
- /* Switch off BCLK_N Divider */
|
|
- snd_soc_component_update_bits(component, AIC32X4_BCLKN,
|
|
- AIC32X4_BCLKEN, 0);
|
|
-
|
|
- /* Switch off MADC Divider */
|
|
- snd_soc_component_update_bits(component, AIC32X4_MADC,
|
|
- AIC32X4_MADCEN, 0);
|
|
-
|
|
- /* Switch off NADC Divider */
|
|
- snd_soc_component_update_bits(component, AIC32X4_NADC,
|
|
- AIC32X4_NADCEN, 0);
|
|
-
|
|
- /* Switch off MDAC Divider */
|
|
- snd_soc_component_update_bits(component, AIC32X4_MDAC,
|
|
- AIC32X4_MDACEN, 0);
|
|
-
|
|
- /* Switch off NDAC Divider */
|
|
- snd_soc_component_update_bits(component, AIC32X4_NDAC,
|
|
- AIC32X4_NDACEN, 0);
|
|
-
|
|
- /* Switch off PLL */
|
|
- snd_soc_component_update_bits(component, AIC32X4_PLLPR,
|
|
- AIC32X4_PLLEN, 0);
|
|
-
|
|
- /* Switch off master clock */
|
|
- clk_disable_unprepare(aic32x4->mclk);
|
|
+ clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
|
|
break;
|
|
case SND_SOC_BIAS_OFF:
|
|
break;
|