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https://github.com/openwrt/openwrt.git
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111 lines
5.0 KiB
Diff
111 lines
5.0 KiB
Diff
From d2536830d8f1ef06afdc84c5ac6e1a70b3a2bc40 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.org>
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Date: Fri, 25 Jan 2019 16:03:31 +0000
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Subject: [PATCH 336/806] usb: dwc_otg: Clean up build warnings on 64bit
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kernels
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No functional changes. Almost all are changes to logging lines.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
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---
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drivers/usb/host/dwc_otg/dwc_otg_driver.c | 3 +--
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drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 2 +-
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drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 19 ++++++++++++++-----
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drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 10 ++++------
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4 files changed, 20 insertions(+), 14 deletions(-)
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--- a/drivers/usb/host/dwc_otg/dwc_otg_driver.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c
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@@ -837,8 +837,7 @@ static int dwc_otg_driver_probe(
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retval = -ENOMEM;
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goto fail;
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}
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- dev_info(&_dev->dev, "base=0x%08x\n",
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- (unsigned)dwc_otg_device->os_dep.base);
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+ dev_info(&_dev->dev, "base=%p\n", dwc_otg_device->os_dep.base);
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#endif
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/*
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--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
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@@ -301,7 +301,7 @@ static int notrace fiq_iso_out_advance(s
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last = 1;
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/* New DMA address - address of bounce buffer referred to in index */
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- hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
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+ hcdma.d32 = (dma_addr_t) blob->channel[n].index[i].buf;
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//hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA);
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//hcdma.d32 += st->channel[n].dma_info.slot_len[i];
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fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
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@@ -1041,8 +1041,8 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd
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* moderately readable array casts.
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*/
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hcd->fiq_dmab = DWC_DMA_ALLOC(dev, (sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);
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- DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d",
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- (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base,
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+ DWC_WARN("FIQ DMA bounce buffers: virt = %px dma = %pad len=%zu",
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+ hcd->fiq_dmab, &hcd->fiq_state->dma_base,
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sizeof(struct fiq_dma_channel) * num_channels);
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DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);
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@@ -1522,9 +1522,12 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h
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/*
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* Set dma_regs to bounce buffer. FIQ will update the
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* state depending on transaction progress.
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+ * Pointer arithmetic on hcd->fiq_state->dma_base (a dma_addr_t)
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+ * to point it to the correct offset in the allocated buffers.
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*/
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blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
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- st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
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+ st->hcdma_copy.d32 = (dma_addr_t) blob->channel[hc->hc_num].index[0].buf;
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+
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/* Calculate the max number of CSPLITS such that the FIQ can time out
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* a transaction if it fails.
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*/
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@@ -1571,9 +1574,15 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h
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st->nrpackets = i;
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}
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ptr = qtd->urb->buf + frame_desc->offset;
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- /* Point the HC at the DMA address of the bounce buffers */
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+ /*
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+ * Point the HC at the DMA address of the bounce buffers
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+ *
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+ * Pointer arithmetic on hcd->fiq_state->dma_base (a
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+ * dma_addr_t) to point it to the correct offset in the
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+ * allocated buffers.
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+ */
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blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
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- st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
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+ st->hcdma_copy.d32 = (dma_addr_t) blob->channel[hc->hc_num].index[0].buf;
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/* fixup xfersize to the actual packet size */
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st->hctsiz_copy.b.pid = 0;
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
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@@ -454,11 +454,9 @@ static void hcd_init_fiq(void *cookie)
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DWC_ERROR("Can't claim FIQ");
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BUG();
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}
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- DWC_WARN("FIQ on core %d at 0x%08x",
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- smp_processor_id(),
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- (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
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- DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
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- set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
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+ DWC_WARN("FIQ on core %d", smp_processor_id());
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+ DWC_WARN("FIQ ASM at %px length %d", &_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
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+ set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
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memset(®s,0,sizeof(regs));
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regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
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@@ -483,7 +481,7 @@ static void hcd_init_fiq(void *cookie)
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dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c;
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dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
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dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
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- DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
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+ DWC_WARN("MPHI regs_base at %px", dwc_otg_hcd->fiq_state->mphi_regs.base);
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//Enable mphi peripheral
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writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
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#ifdef DEBUG
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