mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
df3ad130d5
Replace all the custom patches with the backported upstream version Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> [refresh patches] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
105 lines
3.2 KiB
Diff
105 lines
3.2 KiB
Diff
From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001
|
|
From: Ajay Kishore <akisho@codeaurora.org>
|
|
Date: Fri, 27 Mar 2020 23:32:08 +0100
|
|
Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
|
|
|
|
For IPQ806x targets, TZ protects the registers that are used to
|
|
configure the routing of interrupts to a target processor.
|
|
To resolve this, this patch uses scm call to route GPIO interrupts
|
|
to application processor. Also the scm call interface is changed.
|
|
|
|
Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
|
|
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
|
Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com
|
|
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
---
|
|
drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------
|
|
1 file changed, 37 insertions(+), 6 deletions(-)
|
|
|
|
(limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
|
|
|
|
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
|
|
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
|
|
@@ -22,6 +22,8 @@
|
|
#include <linux/reboot.h>
|
|
#include <linux/pm.h>
|
|
#include <linux/log2.h>
|
|
+#include <linux/qcom_scm.h>
|
|
+#include <linux/io.h>
|
|
|
|
#include "../core.h"
|
|
#include "../pinconf.h"
|
|
@@ -57,6 +59,8 @@ struct msm_pinctrl {
|
|
struct irq_chip irq_chip;
|
|
int irq;
|
|
|
|
+ bool intr_target_use_scm;
|
|
+
|
|
raw_spinlock_t lock;
|
|
|
|
DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
|
|
@@ -64,6 +68,7 @@ struct msm_pinctrl {
|
|
|
|
const struct msm_pinctrl_soc_data *soc;
|
|
void __iomem *regs[MAX_NR_TILES];
|
|
+ u32 phys_base[MAX_NR_TILES];
|
|
};
|
|
|
|
#define MSM_ACCESSOR(name) \
|
|
@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
|
|
else
|
|
clear_bit(d->hwirq, pctrl->dual_edge_irqs);
|
|
|
|
- /* Route interrupts to application cpu */
|
|
- val = msm_readl_intr_target(pctrl, g);
|
|
- val &= ~(7 << g->intr_target_bit);
|
|
- val |= g->intr_target_kpss_val << g->intr_target_bit;
|
|
- msm_writel_intr_target(val, pctrl, g);
|
|
+ /* Route interrupts to application cpu.
|
|
+ * With intr_target_use_scm interrupts are routed to
|
|
+ * application cpu using scm calls.
|
|
+ */
|
|
+ if (pctrl->intr_target_use_scm) {
|
|
+ u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
|
|
+ int ret;
|
|
+
|
|
+ qcom_scm_io_readl(addr, &val);
|
|
+
|
|
+ val &= ~(7 << g->intr_target_bit);
|
|
+ val |= g->intr_target_kpss_val << g->intr_target_bit;
|
|
+
|
|
+ ret = qcom_scm_io_writel(addr, val);
|
|
+ if (ret)
|
|
+ dev_err(pctrl->dev,
|
|
+ "Failed routing %lu interrupt to Apps proc",
|
|
+ d->hwirq);
|
|
+ } else {
|
|
+ val = msm_readl_intr_target(pctrl, g);
|
|
+ val &= ~(7 << g->intr_target_bit);
|
|
+ val |= g->intr_target_kpss_val << g->intr_target_bit;
|
|
+ msm_writel_intr_target(val, pctrl, g);
|
|
+ }
|
|
|
|
/* Update configuration for gpio.
|
|
* RAW_STATUS_EN is left on for all gpio irqs. Due to the
|
|
@@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de
|
|
pctrl->dev = &pdev->dev;
|
|
pctrl->soc = soc_data;
|
|
pctrl->chip = msm_gpio_template;
|
|
+ pctrl->intr_target_use_scm = of_device_is_compatible(
|
|
+ pctrl->dev->of_node,
|
|
+ "qcom,ipq8064-pinctrl");
|
|
|
|
raw_spin_lock_init(&pctrl->lock);
|
|
|
|
@@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de
|
|
pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(pctrl->regs[0]))
|
|
return PTR_ERR(pctrl->regs[0]);
|
|
+
|
|
+ pctrl->phys_base[0] = res->start;
|
|
}
|
|
|
|
msm_pinctrl_setup_pm_reset(pctrl);
|