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f621b53951
Refresh patches. Remove upstreamed patches: - ar7/002-MIPS-AR7-ensure-the-port-type-s-FCR-value-is-used.patch - backport/040-crypto-fix-typo-in-KPP-dependency-of-CRYPTO_ECDH.patch Remove layerscape/819-Revert-dmaengine-dmatest-move-callback-wait-queue-to.patch, it is superseded by upstream commit 297c7cc4b5651b174a62925b6c961085f04979fd. Remove pending/650-pppoe_header_pad.patch, it is superseded by upstream commit 1bd21b158e07e0b8c5a2ce832305a0ebfe42c480. Update patches that no longer apply: - ar71xx/004-register_gpio_driver_earlier.patch - hack/204-module_strip.patch - pending/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch Fixes CVE-2017-8824. Compile-tested: ar71xx. Runtime-tested: ar71xx. Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
44 lines
1.4 KiB
Diff
44 lines
1.4 KiB
Diff
From 8b61a1a33e41456ebeafa0ebe7ec0fccf859861e Mon Sep 17 00:00:00 2001
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From: Nikolay Martynov <mar.kolya@gmail.com>
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Date: Wed, 25 Nov 2015 20:43:46 -0500
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Subject: [PATCH] mtd: nand: Fix Spansion sparearea size detection
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According to datasheet S34ML02G2 and S34ML04G2 have
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larger sparea area size than was detected.
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Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com>
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---
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drivers/mtd/nand/nand_base.c | 9 +++++++++
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1 file changed, 9 insertions(+)
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--- a/drivers/mtd/nand/nand_base.c
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+++ b/drivers/mtd/nand/nand_base.c
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@@ -3856,6 +3856,7 @@ static void nand_decode_ext_id(struct mt
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/*
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* Field definitions are in the following datasheets:
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* Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
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+ * Spansion S34ML02G2 (p.33)
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* New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
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* Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
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*
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@@ -3953,6 +3954,19 @@ static void nand_decode_ext_id(struct mt
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*busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
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/*
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+ * Spansion S34ML0[24]G2 have oobsize twice as large
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+ * as S34ML01G2 encoded in the same bit. We
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+ * differinciate them by their ID length
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+ */
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+ if (id_data[0] == NAND_MFR_AMD
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+ && (id_data[1] == 0xda
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+ || id_data[1] == 0xdc
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+ || id_data[1] == 0xca
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+ || id_data[1] == 0xcc)) {
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+ mtd->oobsize *= 2;
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+ }
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+
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+ /*
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* Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
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* 512B page. For Toshiba SLC, we decode the 5th/6th byte as
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* follows:
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