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188 lines
4.6 KiB
Diff
188 lines
4.6 KiB
Diff
From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001
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From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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Date: Thu, 6 Jun 2019 16:29:04 +0800
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Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629
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Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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---
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arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++
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arch/arm/boot/dts/mt7629-lynx-rfb.dts | 45 ++++++++++++++++++++++++++++++++
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arch/arm/boot/dts/mt7629.dtsi | 22 ++++++++++++++++
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drivers/spi/spi-mtk-snfi.c | 12 +++++++++
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3 files changed, 79 insertions(+)
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diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts
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index 8043238fe..ef140623e 100755
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--- a/arch/arm/boot/dts/mt7629-rfb.dts
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+++ b/arch/arm/boot/dts/mt7629-rfb.dts
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@@ -258,6 +258,51 @@
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};
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};
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+&bch {
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+ status = "okay";
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+};
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+
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+&snfi {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&serial_nand_pins>;
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+ status = "okay";
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+
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+ spi_nand@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "spi-nand";
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+ spi-max-frequency = <104000000>;
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+ reg = <0>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "Bootloader";
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+ reg = <0x00000 0x0100000>;
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+ read-only;
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+ };
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+
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+ partition@100000 {
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+ label = "Config";
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+ reg = <0x100000 0x0040000>;
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+ };
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+
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+ partition@140000 {
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+ label = "factory";
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+ reg = <0x140000 0x0080000>;
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+ };
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+
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+ partition@1c0000 {
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+ label = "firmware";
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+ reg = <0x1c0000 0x1000000>;
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+ };
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+ };
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+ };
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+};
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+
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&spi {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
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index 53f47796b..c7bd5fc9b 100755
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--- a/arch/arm/boot/dts/mt7629.dtsi
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+++ b/arch/arm/boot/dts/mt7629.dtsi
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@@ -259,6 +259,28 @@
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status = "disabled";
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};
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+ bch: ecc@1100e000 {
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+ compatible = "mediatek,mt7622-ecc";
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+ reg = <0x1100e000 0x1000>;
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+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_NFIECC_PD>;
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+ clock-names = "nfiecc_clk";
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+ status = "disabled";
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+ };
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+
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+ snfi: spi@1100d000 {
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+ compatible = "mediatek,mt7629-snfi";
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+ reg = <0x1100d000 0x1000>;
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_NFI_PD>,
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+ <&pericfg CLK_PERI_SNFI_PD>;
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+ clock-names = "nfi_clk", "spi_clk";
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+ ecc-engine = <&bch>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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spi: spi@1100a000 {
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compatible = "mediatek,mt7629-spi",
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"mediatek,mt7622-spi";
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diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c
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index cd600d9fb..113f541e6 100644
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--- a/drivers/spi/spi-mtk-snfi.c
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+++ b/drivers/spi/spi-mtk-snfi.c
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@@ -1029,8 +1029,20 @@ static const struct mtk_snfi_caps snfi_mt7622 = {
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.bad_mark_swap = 0,
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};
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+static const struct mtk_snfi_caps snfi_mt7629 = {
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+ .spare_size = spare_size_mt7622,
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+ .num_spare_size = 4,
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+ .nand_sec_size = 512,
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+ .nand_fdm_size = 8,
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+ .nand_fdm_ecc_size = 1,
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+ .ecc_parity_bits = 13,
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+ .pageformat_spare_shift = 4,
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+ .bad_mark_swap = 1,
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+};
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+
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static const struct of_device_id mtk_snfi_id_table[] = {
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{ .compatible = "mediatek,mt7622-snfi", .data = &snfi_mt7622, },
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+ { .compatible = "mediatek,mt7629-snfi", .data = &snfi_mt7629, },
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{ /* sentinel */ }
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};
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--
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2.21.0
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diff --git a/arch/arm/boot/dts/mt7629-lynx-rfb.dts b/arch/arm/boot/dts/mt7629-lynx-rfb.dts
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index f3fadd3..895d6c4 100755
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--- a/arch/arm/boot/dts/mt7629-lynx-rfb.dts
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+++ b/arch/arm/boot/dts/mt7629-lynx-rfb.dts
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@@ -278,6 +278,52 @@
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};
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};
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+&bch {
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+ status = "okay";
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+};
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+
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+&snfi {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&serial_nand_pins>;
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+ status = "okay";
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+
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+ spi_nand@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "spi-nand";
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+ spi-max-frequency = <104000000>;
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+ reg = <0>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "Bootloader";
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+ reg = <0x00000 0x0100000>;
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+ read-only;
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+ };
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+
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+ partition@100000 {
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+ label = "Config";
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+ reg = <0x100000 0x0040000>;
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+ };
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+
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+ partition@140000 {
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+ label = "factory";
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+ reg = <0x140000 0x0080000>;
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+ };
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+
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+ partition@1c0000 {
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+ label = "firmware";
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+ reg = <0x1c0000 0x1000000>;
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+ };
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+
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+ };
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+ };
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+};
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+
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&spi {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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