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121 lines
3.9 KiB
Diff
121 lines
3.9 KiB
Diff
From c5f9d78ec34de15732bcbff52bedba7a840e42b2 Mon Sep 17 00:00:00 2001
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From: Annaliese McDermond <nh6z@nh6z.net>
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Date: Thu, 21 Mar 2019 17:58:46 -0700
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Subject: [PATCH 400/806] ASoC: tlv320aic32x4: Model CODEC_CLKIN in CCF
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commit fd2df3aeafa4b4cc468d58e147e0822967034b71 upstream.
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Model and manage codec clock input as a component in the Core
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Clock Framework. This should allow us to do some more complex
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clock management and power control. Also, some of the
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on-board chip clocks can be exposed to the outside, and this
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change will make those clocks easier to consume by other
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parts of the kernel.
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Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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sound/soc/codecs/tlv320aic32x4-clk.c | 34 ++++++++++++++++++++++++++++
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sound/soc/codecs/tlv320aic32x4.c | 18 +++++++++++----
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2 files changed, 47 insertions(+), 5 deletions(-)
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--- a/sound/soc/codecs/tlv320aic32x4-clk.c
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+++ b/sound/soc/codecs/tlv320aic32x4-clk.c
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@@ -265,6 +265,30 @@ static const struct clk_ops aic32x4_pll_
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.get_parent = clk_aic32x4_pll_get_parent,
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};
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+static int clk_aic32x4_codec_clkin_set_parent(struct clk_hw *hw, u8 index)
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+{
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+ struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
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+
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+ return regmap_update_bits(mux->regmap,
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+ AIC32X4_CLKMUX,
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+ AIC32X4_CODEC_CLKIN_MASK, index << AIC32X4_CODEC_CLKIN_SHIFT);
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+}
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+
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+static u8 clk_aic32x4_codec_clkin_get_parent(struct clk_hw *hw)
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+{
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+ struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
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+ unsigned int val;
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+
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+ regmap_read(mux->regmap, AIC32X4_CLKMUX, &val);
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+
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+ return (val & AIC32X4_CODEC_CLKIN_MASK) >> AIC32X4_CODEC_CLKIN_SHIFT;
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+}
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+
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+static const struct clk_ops aic32x4_codec_clkin_ops = {
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+ .set_parent = clk_aic32x4_codec_clkin_set_parent,
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+ .get_parent = clk_aic32x4_codec_clkin_get_parent,
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+};
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+
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static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
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{
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.name = "pll",
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@@ -274,6 +298,14 @@ static struct aic32x4_clkdesc aic32x4_cl
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.ops = &aic32x4_pll_ops,
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.reg = 0,
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},
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+ {
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+ .name = "codec_clkin",
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+ .parent_names =
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+ (const char *[]) { "mclk", "bclk", "gpio", "pll" },
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+ .num_parents = 4,
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+ .ops = &aic32x4_codec_clkin_ops,
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+ .reg = 0,
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+ },
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};
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static struct clk *aic32x4_register_clk(struct device *dev,
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@@ -314,6 +346,8 @@ int aic32x4_register_clocks(struct devic
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*/
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aic32x4_clkdesc_array[0].parent_names =
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(const char* []) { mclk_name, "bclk", "gpio", "din" };
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+ aic32x4_clkdesc_array[1].parent_names =
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+ (const char *[]) { mclk_name, "bclk", "gpio", "pll" };
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for (i = 0; i < ARRAY_SIZE(aic32x4_clkdesc_array); ++i)
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aic32x4_register_clk(dev, &aic32x4_clkdesc_array[i]);
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--- a/sound/soc/codecs/tlv320aic32x4.c
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+++ b/sound/soc/codecs/tlv320aic32x4.c
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@@ -737,12 +737,9 @@ static int aic32x4_setup_clocks(struct s
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aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
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- /* PLL as CODEC_CLKIN */
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- snd_soc_component_update_bits(component, AIC32X4_CLKMUX,
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- AIC32X4_CODEC_CLKIN_MASK,
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- AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
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/* DAC_MOD_CLK as BDIV_CLKIN */
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- snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
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+ snd_soc_component_update_bits(component, AIC32X4_IFACE3,
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+ AIC32X4_BDIVCLK_MASK,
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AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
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/* NDAC divider value */
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@@ -989,6 +986,15 @@ static int aic32x4_component_probe(struc
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{
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struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
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u32 tmp_reg;
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+ int ret;
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+
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+ struct clk_bulk_data clocks[] = {
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+ { .id = "codec_clkin" },
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+ };
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+
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+ ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
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+ if (ret)
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+ return ret;
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if (gpio_is_valid(aic32x4->rstn_gpio)) {
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ndelay(10);
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@@ -1000,6 +1006,8 @@ static int aic32x4_component_probe(struc
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if (aic32x4->setup)
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aic32x4_setup_gpios(component);
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+ clk_set_parent(clocks[0].clk, clocks[1].clk);
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+
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/* Power platform configuration */
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if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
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snd_soc_component_write(component, AIC32X4_MICBIAS,
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