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d41d9befb9
Add u-boot bootloader based on 2023.01 to support D1-based boards, currently: - Dongshan Nezha STU - LicheePi RV Dock - MangoPi MQ-Pro - Nezha D1 Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
119 lines
3.8 KiB
Diff
119 lines
3.8 KiB
Diff
From 4df80766531bc35510981ebc5ea0bb07264beac9 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 8 Aug 2021 19:31:20 -0500
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Subject: [PATCH 81/90] mmc: sunxi: Hack up the driver for the D1
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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arch/riscv/include/asm/io.h | 1 +
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drivers/mmc/sunxi_mmc.c | 29 +++++++++++++++++++++++++----
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drivers/mmc/sunxi_mmc.h | 2 --
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3 files changed, 26 insertions(+), 6 deletions(-)
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--- a/arch/riscv/include/asm/io.h
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+++ b/arch/riscv/include/asm/io.h
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@@ -85,6 +85,7 @@ static inline u16 readw(const volatile v
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return val;
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}
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+#define readl_relaxed readl
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static inline u32 readl(const volatile void __iomem *addr)
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{
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u32 val;
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--- a/drivers/mmc/sunxi_mmc.c
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+++ b/drivers/mmc/sunxi_mmc.c
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@@ -23,9 +23,9 @@
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#include <reset.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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+#if !CONFIG_IS_ENABLED(DM_MMC)
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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-#if !CONFIG_IS_ENABLED(DM_MMC)
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#include <asm/arch/mmc.h>
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#endif
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#include <linux/delay.h>
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@@ -36,6 +36,23 @@
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#define CCM_MMC_CTRL_MODE_SEL_NEW 0
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#endif
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+#include "../../arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h"
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+
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+unsigned int clock_get_pll6(void)
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+{
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+ uint32_t rval = readl((void *)0x2001020);
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+
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+ int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
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+ int m = ((rval >> 1) & 0x1) + 1;
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+ int p0 = ((rval >> 16) & 0x7) + 1;
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+ /* The register defines PLL6-2X, not plain PLL6 */
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+ uint32_t freq = 24000000UL * n / m / p0;
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+
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+ printf("PLL reg = 0x%08x, freq = %d\n", rval, freq);
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+
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+ return freq;
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+}
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+
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struct sunxi_mmc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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@@ -60,7 +77,8 @@ static bool sunxi_mmc_can_calibrate(void
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return IS_ENABLED(CONFIG_MACH_SUN50I) ||
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IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
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IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
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- IS_ENABLED(CONFIG_MACH_SUN8I_R40);
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+ IS_ENABLED(CONFIG_MACH_SUN8I_R40) ||
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+ IS_ENABLED(CONFIG_TARGET_SUN20I_D1);
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}
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static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
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@@ -194,7 +212,7 @@ static int mmc_config_clock(struct sunxi
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rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
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writel(rval, &priv->reg->clkcr);
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-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
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+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_TARGET_SUN20I_D1)
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/* A64 supports calibration of delays on MMC controller and we
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* have to set delay of zero before starting calibration.
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* Allwinner BSP driver sets a delay only in the case of
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@@ -622,7 +640,8 @@ static unsigned get_mclk_offset(void)
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if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
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return 0x410;
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- if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
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+ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
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+ IS_ENABLED(CONFIG_TARGET_SUN20I_D1))
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return 0x830;
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return 0x88;
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@@ -662,6 +681,7 @@ static int sunxi_mmc_probe(struct udevic
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return ret;
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ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node);
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+#define SUNXI_MMC0_BASE 0x4020000
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priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
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priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
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@@ -703,6 +723,7 @@ static const struct udevice_id sunxi_mmc
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{ .compatible = "allwinner,sun7i-a20-mmc" },
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{ .compatible = "allwinner,sun8i-a83t-emmc" },
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{ .compatible = "allwinner,sun9i-a80-mmc" },
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+ { .compatible = "allwinner,sun20i-d1-mmc" },
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{ .compatible = "allwinner,sun50i-a64-mmc" },
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{ .compatible = "allwinner,sun50i-a64-emmc" },
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{ .compatible = "allwinner,sun50i-h6-mmc" },
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--- a/drivers/mmc/sunxi_mmc.h
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+++ b/drivers/mmc/sunxi_mmc.h
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@@ -45,11 +45,9 @@ struct sunxi_mmc {
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u32 chda; /* 0x90 */
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u32 cbda; /* 0x94 */
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u32 res2[26];
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-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
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u32 res3[17];
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u32 samp_dl;
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u32 res4[46];
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-#endif
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u32 fifo; /* 0x100 / 0x200 FIFO access address */
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};
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