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f80272dd9c
Refreshed all patches. Remove upstreamed: - 302-0002-dmaengine-dw-implement-per-channel-protection-contro.patch Fixes: - CVE-2019-19332 Compile-tested on: cns3xxx Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
151 lines
5.1 KiB
Diff
151 lines
5.1 KiB
Diff
From 1e932b627e79aa2c70e2c7278e4ac930303faa3f Mon Sep 17 00:00:00 2001
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From: Christian Lamparter <chunkeey@gmail.com>
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Date: Thu, 21 Dec 2017 15:09:18 +0100
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Subject: [PATCH 2/6] crypto: crypto4xx - support Revision B parts
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This patch adds support for the crypto4xx RevB cores
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found in the 460EX, 460SX and later cores (like the APM821xx).
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Without this patch, the crypto4xx driver will not be
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able to process any offloaded requests and simply hang
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indefinitely.
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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---
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drivers/crypto/amcc/crypto4xx_core.c | 48 +++++++++++++++++++++++++++++----
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drivers/crypto/amcc/crypto4xx_core.h | 1 +
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drivers/crypto/amcc/crypto4xx_reg_def.h | 4 ++-
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3 files changed, 47 insertions(+), 6 deletions(-)
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--- a/drivers/crypto/amcc/crypto4xx_core.c
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+++ b/drivers/crypto/amcc/crypto4xx_core.c
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@@ -128,7 +128,14 @@ static void crypto4xx_hw_init(struct cry
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writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
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writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
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writel(PPC4XX_INT_CFG, dev->ce_base + CRYPTO4XX_INT_CFG);
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- writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN);
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+ if (dev->is_revb) {
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+ writel(PPC4XX_INT_TIMEOUT_CNT_REVB << 10,
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+ dev->ce_base + CRYPTO4XX_INT_TIMEOUT_CNT);
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+ writel(PPC4XX_PD_DONE_INT | PPC4XX_TMO_ERR_INT,
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+ dev->ce_base + CRYPTO4XX_INT_EN);
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+ } else {
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+ writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN);
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+ }
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}
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int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size)
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@@ -1075,18 +1082,29 @@ static void crypto4xx_bh_tasklet_cb(unsi
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/**
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* Top Half of isr.
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*/
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-static irqreturn_t crypto4xx_ce_interrupt_handler(int irq, void *data)
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+static inline irqreturn_t crypto4xx_interrupt_handler(int irq, void *data,
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+ u32 clr_val)
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{
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struct device *dev = (struct device *)data;
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struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
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- writel(PPC4XX_INTERRUPT_CLR,
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- core_dev->dev->ce_base + CRYPTO4XX_INT_CLR);
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+ writel(clr_val, core_dev->dev->ce_base + CRYPTO4XX_INT_CLR);
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tasklet_schedule(&core_dev->tasklet);
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return IRQ_HANDLED;
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}
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+static irqreturn_t crypto4xx_ce_interrupt_handler(int irq, void *data)
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+{
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+ return crypto4xx_interrupt_handler(irq, data, PPC4XX_INTERRUPT_CLR);
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+}
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+
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+static irqreturn_t crypto4xx_ce_interrupt_handler_revb(int irq, void *data)
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+{
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+ return crypto4xx_interrupt_handler(irq, data, PPC4XX_INTERRUPT_CLR |
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+ PPC4XX_TMO_ERR_INT);
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+}
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+
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/**
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* Supported Crypto Algorithms
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*/
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@@ -1268,6 +1286,8 @@ static int crypto4xx_probe(struct platfo
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struct resource res;
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struct device *dev = &ofdev->dev;
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struct crypto4xx_core_device *core_dev;
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+ u32 pvr;
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+ bool is_revb = true;
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rc = of_address_to_resource(ofdev->dev.of_node, 0, &res);
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if (rc)
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@@ -1284,6 +1304,7 @@ static int crypto4xx_probe(struct platfo
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mfdcri(SDR0, PPC405EX_SDR0_SRST) | PPC405EX_CE_RESET);
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mtdcri(SDR0, PPC405EX_SDR0_SRST,
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mfdcri(SDR0, PPC405EX_SDR0_SRST) & ~PPC405EX_CE_RESET);
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+ is_revb = false;
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} else if (of_find_compatible_node(NULL, NULL,
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"amcc,ppc460sx-crypto")) {
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mtdcri(SDR0, PPC460SX_SDR0_SRST,
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@@ -1306,7 +1327,22 @@ static int crypto4xx_probe(struct platfo
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if (!core_dev->dev)
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goto err_alloc_dev;
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+ /*
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+ * Older version of 460EX/GT have a hardware bug.
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+ * Hence they do not support H/W based security intr coalescing
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+ */
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+ pvr = mfspr(SPRN_PVR);
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+ if (is_revb && ((pvr >> 4) == 0x130218A)) {
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+ u32 min = PVR_MIN(pvr);
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+
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+ if (min < 4) {
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+ dev_info(dev, "RevA detected - disable interrupt coalescing\n");
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+ is_revb = false;
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+ }
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+ }
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+
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core_dev->dev->core_dev = core_dev;
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+ core_dev->dev->is_revb = is_revb;
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core_dev->device = dev;
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spin_lock_init(&core_dev->lock);
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INIT_LIST_HEAD(&core_dev->dev->alg_list);
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@@ -1336,7 +1372,9 @@ static int crypto4xx_probe(struct platfo
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/* Register for Crypto isr, Crypto Engine IRQ */
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core_dev->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
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- rc = request_irq(core_dev->irq, crypto4xx_ce_interrupt_handler, 0,
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+ rc = request_irq(core_dev->irq, is_revb ?
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+ crypto4xx_ce_interrupt_handler_revb :
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+ crypto4xx_ce_interrupt_handler, 0,
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core_dev->dev->name, dev);
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if (rc)
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goto err_request_irq;
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--- a/drivers/crypto/amcc/crypto4xx_core.h
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+++ b/drivers/crypto/amcc/crypto4xx_core.h
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@@ -109,6 +109,7 @@ struct crypto4xx_device {
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struct list_head alg_list; /* List of algorithm supported
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by this device */
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struct ratelimit_state aead_ratelimit;
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+ bool is_revb;
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};
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struct crypto4xx_core_device {
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--- a/drivers/crypto/amcc/crypto4xx_reg_def.h
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+++ b/drivers/crypto/amcc/crypto4xx_reg_def.h
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@@ -121,13 +121,15 @@
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#define PPC4XX_PD_SIZE 6
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#define PPC4XX_CTX_DONE_INT 0x2000
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#define PPC4XX_PD_DONE_INT 0x8000
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+#define PPC4XX_TMO_ERR_INT 0x40000
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#define PPC4XX_BYTE_ORDER 0x22222
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#define PPC4XX_INTERRUPT_CLR 0x3ffff
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#define PPC4XX_PRNG_CTRL_AUTO_EN 0x3
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#define PPC4XX_DC_3DES_EN 1
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#define PPC4XX_TRNG_EN 0x00020000
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-#define PPC4XX_INT_DESCR_CNT 4
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+#define PPC4XX_INT_DESCR_CNT 7
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#define PPC4XX_INT_TIMEOUT_CNT 0
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+#define PPC4XX_INT_TIMEOUT_CNT_REVB 0x3FF
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#define PPC4XX_INT_CFG 1
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/**
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* all follow define are ad hoc
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