mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 15:02:32 +00:00
b142587f6e
The existing device tree has incorrect definitions for usb3_0 and usb3_1
and the blocks they depend upon: their addresses and interrupts are
swapped. However, their clocks and resets are not. The result is that
the USB blocks are non-functional if only one of them is enabled.
This fix backports the definitions from mainline Linux 5.15 to
OpenWrt's 5.10 dtsi additions. See the relevant mainline code here:
https://github.com/torvalds/linux/blob/v5.17/arch/arm/boot/dts/qcom-ipq8064.dtsi#L1062-L1148
This fix does not break existing ports. But some ports may have enabled
both USB blocks even thought their board only implements one, because
enabling a single USB block would not have worked before this fix.
This means that revisiting all ports of ipq806x devices that implement
a single USB port is advised. This work must be done by maintainers that
can determine which USB block corresponds to the implemented port on
their hardware.
Note that this fix swaps the names of the hardware ports. This is
unfortunate, but will happen anyway when switching to kernel 5.15. Thus,
it is best to do this ASAP, before users get to depend on port names.
It is strongly recommended that this fix is backported to 22.03 before
its release. This will minimize the number of users affected by the port
name swap.
Signed-off-by: Rodrigo Balerdi <lanchon@gmail.com>
(cherry picked from commit 284f2c2ae0)
847 lines
19 KiB
Diff
847 lines
19 KiB
Diff
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -8,6 +8,8 @@
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#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/mfd/qcom-rpm.h>
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+#include <dt-bindings/clock/qcom,rpmcc.h>
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/ {
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#address-cells = <1>;
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@@ -28,6 +30,16 @@
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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+ clocks = <&kraitcc 0>, <&kraitcc 4>;
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+ clock-names = "cpu", "l2";
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+ clock-latency = <100000>;
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+ cpu-supply = <&smb208_s2a>;
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+ operating-points-v2 = <&opp_table0>;
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+ voltage-tolerance = <5>;
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+ cooling-min-state = <0>;
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+ cooling-max-state = <10>;
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+ #cooling-cells = <2>;
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+ cpu-idle-states = <&CPU_SPC>;
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};
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cpu1: cpu@1 {
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@@ -38,14 +50,350 @@
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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+ clocks = <&kraitcc 1>, <&kraitcc 4>;
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+ clock-names = "cpu", "l2";
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+ clock-latency = <100000>;
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+ cpu-supply = <&smb208_s2b>;
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+ operating-points-v2 = <&opp_table0>;
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+ voltage-tolerance = <5>;
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+ cooling-min-state = <0>;
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+ cooling-max-state = <10>;
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+ #cooling-cells = <2>;
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+ cpu-idle-states = <&CPU_SPC>;
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+ };
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+
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+ idle-states {
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+ CPU_SPC: spc {
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+ compatible = "qcom,idle-state-spc";
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+ status = "disabled";
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+ entry-latency-us = <400>;
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+ exit-latency-us = <900>;
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+ min-residency-us = <3000>;
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+ };
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};
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+ };
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- L2: l2-cache {
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- compatible = "cache";
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- cache-level = <2>;
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+ opp_table_l2: opp_table_l2 {
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+ compatible = "operating-points-v2";
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+
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+ opp-384000000 {
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+ opp-hz = /bits/ 64 <384000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <0>;
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+ };
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+
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+ opp-1000000000 {
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+ opp-hz = /bits/ 64 <1000000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1150000>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <2>;
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+ };
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+ };
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+
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+ opp_table0: opp_table0 {
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+ compatible = "operating-points-v2-kryo-cpu";
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+ nvmem-cells = <&speedbin_efuse>;
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+
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+ /*
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+ * Voltage thresholds are <target min max>
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+ */
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+ opp-384000000 {
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+ opp-hz = /bits/ 64 <384000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
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+ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
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+ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
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+ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <0>;
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+ };
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+
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+ opp-600000000 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
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+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
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+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
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+ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-800000000 {
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+ opp-hz = /bits/ 64 <800000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
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+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
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+ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
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+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1000000000 {
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+ opp-hz = /bits/ 64 <1000000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
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+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
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+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
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+ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
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+ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
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+ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
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+ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <2>;
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+ };
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+
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+ opp-1400000000 {
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+ opp-hz = /bits/ 64 <1400000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
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+ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
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+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
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+ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <2>;
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};
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};
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+ thermal-zones {
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+ tsens_tz_sensor0 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 0>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+
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+ cpu-hot {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor1 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 1>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+
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+ cpu-hot {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor2 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 2>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+
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+ cpu-hot {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor3 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 3>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+
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+ cpu-hot {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor4 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 4>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+
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+ cpu-hot {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor5 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 5>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+
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+ cpu-hot {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor6 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 6>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+
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+ cpu-hot {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor7 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 7>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+
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+ cpu-hot {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor8 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 8>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+
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+ cpu-hot {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor9 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 9>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+
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+ cpu-hot {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor10 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 10>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+
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+ cpu-hot {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+ };
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+ };
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+ };
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+
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memory {
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device_type = "memory";
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reg = <0x0 0x0>;
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@@ -93,6 +441,15 @@
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};
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};
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+ fab-scaling {
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+ compatible = "qcom,fab-scaling";
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+ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
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+ clock-names = "apps-fab-clk", "ddr-fab-clk";
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+ fab_freq_high = <533000000>;
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+ fab_freq_nominal = <400000000>;
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+ cpu_freq_threshold = <1000000000>;
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+ };
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+
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firmware {
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scm {
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compatible = "qcom,scm-ipq806x", "qcom,scm";
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@@ -120,6 +477,78 @@
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reg-names = "lpass-lpaif";
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};
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+ L2: l2-cache {
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+ compatible = "qcom,krait-cache", "cache";
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+ cache-level = <2>;
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+ qcom,saw = <&saw_l2>;
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+
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+ clocks = <&kraitcc 4>;
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+ clock-names = "l2";
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+ l2-supply = <&smb208_s1a>;
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+ operating-points-v2 = <&opp_table_l2>;
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+ };
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+
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+ rpm: rpm@108000 {
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+ compatible = "qcom,rpm-ipq8064";
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+ reg = <0x108000 0x1000>;
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+ qcom,ipc = <&l2cc 0x8 2>;
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+
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+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "ack", "err", "wakeup";
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+
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+ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
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+ clock-names = "ram";
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ rpmcc: clock-controller {
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+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
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+ #clock-cells = <1>;
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+ };
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+
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+ regulators {
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+ compatible = "qcom,rpm-smb208-regulators";
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+
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+ smb208_s1a: s1a {
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+ regulator-min-microvolt = <1050000>;
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+ regulator-max-microvolt = <1150000>;
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+
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+ qcom,switch-mode-frequency = <1200000>;
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+ };
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+
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+ smb208_s1b: s1b {
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+ regulator-min-microvolt = <1050000>;
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+ regulator-max-microvolt = <1150000>;
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+
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+ qcom,switch-mode-frequency = <1200000>;
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+ };
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+
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+ smb208_s2a: s2a {
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+ regulator-min-microvolt = < 800000>;
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+ regulator-max-microvolt = <1250000>;
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+
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+ qcom,switch-mode-frequency = <1200000>;
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+ };
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+
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+ smb208_s2b: s2b {
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+ regulator-min-microvolt = < 800000>;
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+ regulator-max-microvolt = <1250000>;
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+
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+ qcom,switch-mode-frequency = <1200000>;
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+ };
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+ };
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+ };
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+
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+ rng@1a500000 {
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+ compatible = "qcom,prng";
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+ reg = <0x1a500000 0x200>;
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+ clocks = <&gcc PRNG_CLK>;
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+ clock-names = "core";
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+ };
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+
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qcom_pinmux: pinmux@800000 {
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compatible = "qcom,ipq8064-pinctrl";
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reg = <0x800000 0x4000>;
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@@ -160,6 +589,15 @@
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};
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};
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+ i2c4_pins: i2c4_pinmux {
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+ mux {
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+ pins = "gpio12", "gpio13";
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+ function = "gsbi4";
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+ drive-strength = <12>;
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+ bias-disable;
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+ };
|
|
+ };
|
|
+
|
|
spi_pins: spi_pins {
|
|
mux {
|
|
pins = "gpio18", "gpio19", "gpio21";
|
|
@@ -169,6 +607,53 @@
|
|
};
|
|
};
|
|
|
|
+ nand_pins: nand_pins {
|
|
+ disable {
|
|
+ pins = "gpio34", "gpio35", "gpio36",
|
|
+ "gpio37", "gpio38";
|
|
+ function = "nand";
|
|
+ drive-strength = <10>;
|
|
+ bias-disable;
|
|
+ };
|
|
+
|
|
+ pullups {
|
|
+ pins = "gpio39";
|
|
+ function = "nand";
|
|
+ drive-strength = <10>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
+ hold {
|
|
+ pins = "gpio40", "gpio41", "gpio42",
|
|
+ "gpio43", "gpio44", "gpio45",
|
|
+ "gpio46", "gpio47";
|
|
+ function = "nand";
|
|
+ drive-strength = <10>;
|
|
+ bias-bus-hold;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mdio0_pins: mdio0_pins {
|
|
+ mux {
|
|
+ pins = "gpio0", "gpio1";
|
|
+ function = "mdio";
|
|
+ drive-strength = <8>;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rgmii2_pins: rgmii2_pins {
|
|
+ mux {
|
|
+ pins = "gpio27", "gpio28", "gpio29",
|
|
+ "gpio30", "gpio31", "gpio32",
|
|
+ "gpio51", "gpio52", "gpio59",
|
|
+ "gpio60", "gpio61", "gpio62";
|
|
+ function = "rgmii2";
|
|
+ drive-strength = <8>;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
leds_pins: leds_pins {
|
|
mux {
|
|
pins = "gpio7", "gpio8", "gpio9",
|
|
@@ -231,6 +716,17 @@
|
|
clock-output-names = "acpu1_aux";
|
|
};
|
|
|
|
+ l2cc: clock-controller@2011000 {
|
|
+ compatible = "qcom,kpss-gcc", "syscon";
|
|
+ reg = <0x2011000 0x1000>;
|
|
+ clock-output-names = "acpu_l2_aux";
|
|
+ };
|
|
+
|
|
+ kraitcc: clock-controller {
|
|
+ compatible = "qcom,krait-cc-v1";
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+
|
|
saw0: regulator@2089000 {
|
|
compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
|
|
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
|
@@ -243,6 +739,52 @@
|
|
regulator;
|
|
};
|
|
|
|
+ saw_l2: regulator@02012000 {
|
|
+ compatible = "qcom,saw2", "syscon";
|
|
+ reg = <0x02012000 0x1000>;
|
|
+ regulator;
|
|
+ };
|
|
+
|
|
+ sic_non_secure: sic-non-secure@12100000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x12100000 0x10000>;
|
|
+ };
|
|
+
|
|
+ gsbi1: gsbi@12440000 {
|
|
+ compatible = "qcom,gsbi-v1.0.0";
|
|
+ cell-index = <1>;
|
|
+ reg = <0x12440000 0x100>;
|
|
+ clocks = <&gcc GSBI1_H_CLK>;
|
|
+ clock-names = "iface";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ syscon-tcsr = <&tcsr>;
|
|
+
|
|
+ gsbi1_serial: serial@12450000 {
|
|
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
+ reg = <0x12450000 0x100>,
|
|
+ <0x12400000 0x03>;
|
|
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gsbi1_i2c: i2c@12460000 {
|
|
+ compatible = "qcom,i2c-qup-v1.1.1";
|
|
+ reg = <0x12460000 0x1000>;
|
|
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
gsbi2: gsbi@12480000 {
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
cell-index = <2>;
|
|
@@ -368,6 +910,33 @@
|
|
};
|
|
};
|
|
|
|
+ gsbi6: gsbi@16500000 {
|
|
+ status = "disabled";
|
|
+ compatible = "qcom,gsbi-v1.0.0";
|
|
+ cell-index = <6>;
|
|
+ reg = <0x16500000 0x100>;
|
|
+ clocks = <&gcc GSBI6_H_CLK>;
|
|
+ clock-names = "iface";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges;
|
|
+
|
|
+ syscon-tcsr = <&tcsr>;
|
|
+
|
|
+ gsbi6_i2c: i2c@16580000 {
|
|
+ compatible = "qcom,i2c-qup-v1.1.1";
|
|
+ reg = <0x16580000 0x1000>;
|
|
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
+
|
|
+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+ status = "disabled";
|
|
+
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
gsbi7: gsbi@16600000 {
|
|
status = "disabled";
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
@@ -389,6 +958,19 @@
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ gsbi7_i2c: i2c@16680000 {
|
|
+ compatible = "qcom,i2c-qup-v1.1.1";
|
|
+ reg = <0x16680000 0x1000>;
|
|
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
+
|
|
+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+ status = "disabled";
|
|
+
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
};
|
|
|
|
sata_phy: sata-phy@1b400000 {
|
|
@@ -478,6 +1060,95 @@
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
+ sfpb_mutex_block: syscon@1200600 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x01200600 0x100>;
|
|
+ };
|
|
+
|
|
+ hs_phy_0: hs_phy_0 {
|
|
+ compatible = "qcom,ipq806x-usb-phy-hs";
|
|
+ reg = <0x100f8800 0x30>;
|
|
+ clocks = <&gcc USB30_0_UTMI_CLK>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <0>;
|
|
+ };
|
|
+
|
|
+ ss_phy_0: ss_phy_0 {
|
|
+ compatible = "qcom,ipq806x-usb-phy-ss";
|
|
+ reg = <0x100f8830 0x30>;
|
|
+ clocks = <&gcc USB30_0_MASTER_CLK>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <0>;
|
|
+ };
|
|
+
|
|
+ usb3_0: usb3@100f8800 {
|
|
+ compatible = "qcom,dwc3", "syscon";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ reg = <0x100f8800 0x8000>;
|
|
+ clocks = <&gcc USB30_0_MASTER_CLK>;
|
|
+ clock-names = "core";
|
|
+
|
|
+ ranges;
|
|
+
|
|
+ resets = <&gcc USB30_0_MASTER_RESET>;
|
|
+ reset-names = "master";
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ dwc3_0: dwc3@10000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x10000000 0xcd00>;
|
|
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ phys = <&hs_phy_0>, <&ss_phy_0>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ dr_mode = "host";
|
|
+ snps,dis_u3_susphy_quirk;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hs_phy_1: hs_phy_1 {
|
|
+ compatible = "qcom,ipq806x-usb-phy-hs";
|
|
+ reg = <0x110f8800 0x30>;
|
|
+ clocks = <&gcc USB30_1_UTMI_CLK>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <0>;
|
|
+ };
|
|
+
|
|
+ ss_phy_1: ss_phy_1 {
|
|
+ compatible = "qcom,ipq806x-usb-phy-ss";
|
|
+ reg = <0x110f8830 0x30>;
|
|
+ clocks = <&gcc USB30_1_MASTER_CLK>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <0>;
|
|
+ };
|
|
+
|
|
+ usb3_1: usb3@110f8800 {
|
|
+ compatible = "qcom,dwc3", "syscon";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ reg = <0x110f8800 0x8000>;
|
|
+ clocks = <&gcc USB30_1_MASTER_CLK>;
|
|
+ clock-names = "core";
|
|
+
|
|
+ ranges;
|
|
+
|
|
+ resets = <&gcc USB30_1_MASTER_RESET>;
|
|
+ reset-names = "master";
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ dwc3_1: dwc3@11000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x11000000 0xcd00>;
|
|
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ phys = <&hs_phy_1>, <&ss_phy_1>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ dr_mode = "host";
|
|
+ snps,dis_u3_susphy_quirk;
|
|
+ };
|
|
+ };
|
|
+
|
|
pcie0: pci@1b500000 {
|
|
compatible = "qcom,pcie-ipq8064";
|
|
reg = <0x1b500000 0x1000
|
|
@@ -739,6 +1410,59 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ adm_dma: dma@18300000 {
|
|
+ compatible = "qcom,adm";
|
|
+ reg = <0x18300000 0x100000>;
|
|
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #dma-cells = <1>;
|
|
+
|
|
+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+
|
|
+ resets = <&gcc ADM0_RESET>,
|
|
+ <&gcc ADM0_PBUS_RESET>,
|
|
+ <&gcc ADM0_C0_RESET>,
|
|
+ <&gcc ADM0_C1_RESET>,
|
|
+ <&gcc ADM0_C2_RESET>;
|
|
+ reset-names = "clk", "pbus", "c0", "c1", "c2";
|
|
+ qcom,ee = <0>;
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ nand_controller: nand-controller@1ac00000 {
|
|
+ compatible = "qcom,ipq806x-nand";
|
|
+ reg = <0x1ac00000 0x800>;
|
|
+
|
|
+ clocks = <&gcc EBI2_CLK>,
|
|
+ <&gcc EBI2_AON_CLK>;
|
|
+ clock-names = "core", "aon";
|
|
+
|
|
+ dmas = <&adm_dma 3>;
|
|
+ dma-names = "rxtx";
|
|
+ qcom,cmd-crci = <15>;
|
|
+ qcom,data-crci = <3>;
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ mdio0: mdio@37000000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ compatible = "qcom,ipq8064-mdio", "syscon";
|
|
+ reg = <0x37000000 0x200000>;
|
|
+ resets = <&gcc GMAC_CORE1_RESET>;
|
|
+ reset-names = "stmmaceth";
|
|
+ clocks = <&gcc GMAC_CORE1_CLK>;
|
|
+ clock-names = "stmmaceth";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
vsdcc_fixed: vsdcc-regulator {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "SDCC Power";
|
|
@@ -814,4 +1538,17 @@
|
|
};
|
|
};
|
|
};
|
|
+
|
|
+ sfpb_mutex: sfpb-mutex {
|
|
+ compatible = "qcom,sfpb-mutex";
|
|
+ syscon = <&sfpb_mutex_block 4 4>;
|
|
+
|
|
+ #hwlock-cells = <1>;
|
|
+ };
|
|
+
|
|
+ smem {
|
|
+ compatible = "qcom,smem";
|
|
+ memory-region = <&smem>;
|
|
+ hwlocks = <&sfpb_mutex 3>;
|
|
+ };
|
|
};
|