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c09eb08dad
Import pending patches to support the upcoming Filogic platforms. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
120 lines
3.4 KiB
Diff
120 lines
3.4 KiB
Diff
From 7860bc58c43dfa939d2664be518c28aea591aeef Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 27 Jul 2022 11:38:33 +0800
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Subject: [PATCH 14/31] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs
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This patch add general-purpose timer support for MediaTek MT7981/MT7986.
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These two SoCs uses a newer version of timer with its register definition
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slightly changed.
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Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/timer/mtk_timer.c | 59 ++++++++++++++++++++++++---------------
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1 file changed, 37 insertions(+), 22 deletions(-)
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--- a/drivers/timer/mtk_timer.c
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+++ b/drivers/timer/mtk_timer.c
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@@ -13,24 +13,32 @@
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#include <asm/io.h>
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#include <linux/bitops.h>
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-#define MTK_GPT4_CTRL 0x40
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-#define MTK_GPT4_CLK 0x44
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-#define MTK_GPT4_CNT 0x48
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-
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-#define GPT4_ENABLE BIT(0)
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-#define GPT4_CLEAR BIT(1)
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-#define GPT4_FREERUN GENMASK(5, 4)
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-#define GPT4_CLK_SYS 0x0
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-#define GPT4_CLK_DIV1 0x0
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+#define MTK_GPT4_OFFSET_V1 0x40
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+#define MTK_GPT4_OFFSET_V2 0x80
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+
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+#define MTK_GPT_CON 0x0
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+#define MTK_GPT_V1_CLK 0x4
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+#define MTK_GPT_CNT 0x8
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+
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+#define GPT_ENABLE BIT(0)
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+#define GPT_CLEAR BIT(1)
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+#define GPT_V1_FREERUN GENMASK(5, 4)
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+#define GPT_V2_FREERUN GENMASK(6, 5)
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+
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+enum mtk_gpt_ver {
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+ MTK_GPT_V1,
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+ MTK_GPT_V2
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+};
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struct mtk_timer_priv {
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void __iomem *base;
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+ unsigned int gpt4_offset;
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};
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static u64 mtk_timer_get_count(struct udevice *dev)
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{
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struct mtk_timer_priv *priv = dev_get_priv(dev);
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- u32 val = readl(priv->base + MTK_GPT4_CNT);
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+ u32 val = readl(priv->base + priv->gpt4_offset + MTK_GPT_CNT);
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return timer_conv_64(val);
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}
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@@ -40,12 +48,27 @@ static int mtk_timer_probe(struct udevic
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct mtk_timer_priv *priv = dev_get_priv(dev);
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struct clk clk, parent;
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- int ret;
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+ int ret, gpt_ver;
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priv->base = dev_read_addr_ptr(dev);
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+ gpt_ver = dev_get_driver_data(dev);
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+
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if (!priv->base)
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return -ENOENT;
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+ if (gpt_ver == MTK_GPT_V2) {
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+ priv->gpt4_offset = MTK_GPT4_OFFSET_V2;
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+
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+ writel(GPT_V2_FREERUN | GPT_CLEAR | GPT_ENABLE,
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+ priv->base + priv->gpt4_offset + MTK_GPT_CON);
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+ } else {
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+ priv->gpt4_offset = MTK_GPT4_OFFSET_V1;
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+
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+ writel(GPT_V1_FREERUN | GPT_CLEAR | GPT_ENABLE,
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+ priv->base + priv->gpt4_offset + MTK_GPT_CON);
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+ writel(0, priv->base + priv->gpt4_offset + MTK_GPT_V1_CLK);
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+ }
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+
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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@@ -61,16 +84,6 @@ static int mtk_timer_probe(struct udevic
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if (!uc_priv->clock_rate)
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return -EINVAL;
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- /*
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- * Initialize the timer:
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- * 1. set clock source to system clock with clock divider setting to 1
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- * 2. set timer mode to free running
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- * 3. reset timer counter to 0 then enable the timer
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- */
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- writel(GPT4_CLK_SYS | GPT4_CLK_DIV1, priv->base + MTK_GPT4_CLK);
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- writel(GPT4_FREERUN | GPT4_CLEAR | GPT4_ENABLE,
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- priv->base + MTK_GPT4_CTRL);
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-
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return 0;
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}
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@@ -79,8 +92,10 @@ static const struct timer_ops mtk_timer_
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};
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static const struct udevice_id mtk_timer_ids[] = {
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- { .compatible = "mediatek,timer" },
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- { .compatible = "mediatek,mt6577-timer" },
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+ { .compatible = "mediatek,timer", .data = MTK_GPT_V1 },
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+ { .compatible = "mediatek,mt6577-timer", .data = MTK_GPT_V1 },
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+ { .compatible = "mediatek,mt7981-timer", .data = MTK_GPT_V2 },
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+ { .compatible = "mediatek,mt7986-timer", .data = MTK_GPT_V2 },
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{ }
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};
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