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bb1eb5e8e6
1. Add support for Marvell CN9130 SoC
2. Add support for CP115,and create an armada-cp11x.dtsi file which will be used to instantiate both CP110 and CP115
3. Add support for AP807/AP807-quad,AP807 is a major component of CN9130 SoC series
4. Drop PCIe I/O ranges from CP11x file and externalize PCIe macros from CP11x file
Signed-off-by: Ian Chang <ianchang@ieiworld.com>
(cherry picked from commit c98ddf0f01)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
938 lines
22 KiB
Diff
938 lines
22 KiB
Diff
From 7409b155562cc19b929b57692b334c5758ffc75d Mon Sep 17 00:00:00 2001
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From: Konstantin Porotchkin <kostap@marvell.com>
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Date: Fri, 4 Oct 2019 16:27:22 +0200
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Subject: [PATCH] arm64: dts: marvell: Prepare the introduction of AP807 based
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SoCs
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Prepare the support for Marvell AP807 die. This die is very similar to
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AP806 but uses different DDR PHY. AP807 is a major component of CN9130
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SoC series.
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Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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---
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arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 448 +----------------
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arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 456 ++++++++++++++++++
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2 files changed, 458 insertions(+), 446 deletions(-)
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create mode 100644 arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
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--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
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@@ -5,454 +5,10 @@
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* Device Tree file for Marvell Armada AP806.
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*/
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-#include <dt-bindings/interrupt-controller/arm-gic.h>
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-#include <dt-bindings/thermal/thermal.h>
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-
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-/dts-v1/;
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+#define AP_NAME ap806
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+#include "armada-ap80x.dtsi"
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/ {
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model = "Marvell Armada AP806";
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compatible = "marvell,armada-ap806";
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- #address-cells = <2>;
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- #size-cells = <2>;
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-
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- aliases {
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- serial0 = &uart0;
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- serial1 = &uart1;
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- gpio0 = &ap_gpio;
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- spi0 = &spi0;
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- };
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-
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- psci {
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- compatible = "arm,psci-0.2";
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- method = "smc";
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- };
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-
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- reserved-memory {
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- #address-cells = <2>;
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- #size-cells = <2>;
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- ranges;
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-
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- /*
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- * This area matches the mapping done with a
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- * mainline U-Boot, and should be updated by the
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- * bootloader.
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- */
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-
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- psci-area@4000000 {
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- reg = <0x0 0x4000000 0x0 0x200000>;
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- no-map;
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- };
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- };
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-
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- ap806 {
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- #address-cells = <2>;
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- #size-cells = <2>;
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- compatible = "simple-bus";
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- interrupt-parent = <&gic>;
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- ranges;
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-
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- config-space@f0000000 {
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- #address-cells = <1>;
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- #size-cells = <1>;
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- compatible = "simple-bus";
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- ranges = <0x0 0x0 0xf0000000 0x1000000>;
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-
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- gic: interrupt-controller@210000 {
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- compatible = "arm,gic-400";
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- #interrupt-cells = <3>;
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- #address-cells = <1>;
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- #size-cells = <1>;
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- ranges;
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- interrupt-controller;
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- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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- reg = <0x210000 0x10000>,
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- <0x220000 0x20000>,
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- <0x240000 0x20000>,
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- <0x260000 0x20000>;
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-
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- gic_v2m0: v2m@280000 {
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- compatible = "arm,gic-v2m-frame";
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- msi-controller;
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- reg = <0x280000 0x1000>;
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- arm,msi-base-spi = <160>;
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- arm,msi-num-spis = <32>;
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- };
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- gic_v2m1: v2m@290000 {
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- compatible = "arm,gic-v2m-frame";
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- msi-controller;
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- reg = <0x290000 0x1000>;
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- arm,msi-base-spi = <192>;
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- arm,msi-num-spis = <32>;
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- };
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- gic_v2m2: v2m@2a0000 {
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- compatible = "arm,gic-v2m-frame";
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- msi-controller;
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- reg = <0x2a0000 0x1000>;
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- arm,msi-base-spi = <224>;
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- arm,msi-num-spis = <32>;
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- };
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- gic_v2m3: v2m@2b0000 {
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- compatible = "arm,gic-v2m-frame";
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- msi-controller;
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- reg = <0x2b0000 0x1000>;
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- arm,msi-base-spi = <256>;
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- arm,msi-num-spis = <32>;
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- };
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- };
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-
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- timer {
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- compatible = "arm,armv8-timer";
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- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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- };
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-
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- pmu {
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- compatible = "arm,cortex-a72-pmu";
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- interrupt-parent = <&pic>;
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- interrupts = <17>;
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- };
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-
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- odmi: odmi@300000 {
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- compatible = "marvell,odmi-controller";
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- interrupt-controller;
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- msi-controller;
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- marvell,odmi-frames = <4>;
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- reg = <0x300000 0x4000>,
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- <0x304000 0x4000>,
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- <0x308000 0x4000>,
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- <0x30C000 0x4000>;
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- marvell,spi-base = <128>, <136>, <144>, <152>;
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- };
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-
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- gicp: gicp@3f0040 {
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- compatible = "marvell,ap806-gicp";
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- reg = <0x3f0040 0x10>;
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- marvell,spi-ranges = <64 64>, <288 64>;
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- msi-controller;
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- };
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-
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- pic: interrupt-controller@3f0100 {
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- compatible = "marvell,armada-8k-pic";
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- reg = <0x3f0100 0x10>;
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- #interrupt-cells = <1>;
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- interrupt-controller;
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- interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
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- };
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-
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- sei: interrupt-controller@3f0200 {
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- compatible = "marvell,ap806-sei";
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- reg = <0x3f0200 0x40>;
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- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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- #interrupt-cells = <1>;
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- interrupt-controller;
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- msi-controller;
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- };
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-
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- xor@400000 {
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- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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- reg = <0x400000 0x1000>,
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- <0x410000 0x1000>;
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- msi-parent = <&gic_v2m0>;
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- clocks = <&ap_clk 3>;
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- dma-coherent;
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- };
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-
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- xor@420000 {
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- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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- reg = <0x420000 0x1000>,
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- <0x430000 0x1000>;
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- msi-parent = <&gic_v2m0>;
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- clocks = <&ap_clk 3>;
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- dma-coherent;
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- };
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-
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- xor@440000 {
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- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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- reg = <0x440000 0x1000>,
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- <0x450000 0x1000>;
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- msi-parent = <&gic_v2m0>;
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- clocks = <&ap_clk 3>;
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- dma-coherent;
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- };
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-
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- xor@460000 {
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- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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- reg = <0x460000 0x1000>,
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- <0x470000 0x1000>;
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- msi-parent = <&gic_v2m0>;
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- clocks = <&ap_clk 3>;
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- dma-coherent;
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- };
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-
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- spi0: spi@510600 {
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- compatible = "marvell,armada-380-spi";
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- reg = <0x510600 0x50>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&ap_clk 3>;
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- status = "disabled";
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- };
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-
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- i2c0: i2c@511000 {
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- compatible = "marvell,mv78230-i2c";
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- reg = <0x511000 0x20>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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- timeout-ms = <1000>;
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- clocks = <&ap_clk 3>;
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- status = "disabled";
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- };
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-
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- uart0: serial@512000 {
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- compatible = "snps,dw-apb-uart";
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- reg = <0x512000 0x100>;
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- reg-shift = <2>;
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- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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- reg-io-width = <1>;
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- clocks = <&ap_clk 3>;
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- status = "disabled";
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- };
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-
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- uart1: serial@512100 {
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- compatible = "snps,dw-apb-uart";
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- reg = <0x512100 0x100>;
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- reg-shift = <2>;
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- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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- reg-io-width = <1>;
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- clocks = <&ap_clk 3>;
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- status = "disabled";
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-
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- };
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-
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- watchdog: watchdog@610000 {
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- compatible = "arm,sbsa-gwdt";
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- reg = <0x610000 0x1000>, <0x600000 0x1000>;
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- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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- };
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-
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- ap_sdhci0: sdhci@6e0000 {
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- compatible = "marvell,armada-ap806-sdhci";
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- reg = <0x6e0000 0x300>;
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- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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- clock-names = "core";
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- clocks = <&ap_clk 4>;
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- dma-coherent;
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- marvell,xenon-phy-slow-mode;
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- status = "disabled";
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- };
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-
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- ap_syscon0: system-controller@6f4000 {
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- compatible = "syscon", "simple-mfd";
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- reg = <0x6f4000 0x2000>;
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-
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- ap_clk: clock {
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- compatible = "marvell,ap806-clock";
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- #clock-cells = <1>;
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- };
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-
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- ap_pinctrl: pinctrl {
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- compatible = "marvell,ap806-pinctrl";
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-
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- uart0_pins: uart0-pins {
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- marvell,pins = "mpp11", "mpp19";
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- marvell,function = "uart0";
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- };
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- };
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-
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- ap_gpio: gpio@1040 {
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- compatible = "marvell,armada-8k-gpio";
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- offset = <0x1040>;
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- ngpios = <20>;
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- gpio-controller;
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- #gpio-cells = <2>;
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- gpio-ranges = <&ap_pinctrl 0 0 20>;
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- };
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- };
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-
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- ap_syscon1: system-controller@6f8000 {
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- compatible = "syscon", "simple-mfd";
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- reg = <0x6f8000 0x1000>;
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- #address-cells = <1>;
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- #size-cells = <1>;
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-
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- cpu_clk: clock-cpu@278 {
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- compatible = "marvell,ap806-cpu-clock";
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- clocks = <&ap_clk 0>, <&ap_clk 1>;
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- #clock-cells = <1>;
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- reg = <0x278 0xa30>;
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- };
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-
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- ap_thermal: thermal-sensor@80 {
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- compatible = "marvell,armada-ap806-thermal";
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- reg = <0x80 0x10>;
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- interrupt-parent = <&sei>;
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- interrupts = <18>;
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- #thermal-sensor-cells = <1>;
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- };
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- };
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- };
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- };
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-
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- /*
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- * The thermal IP features one internal sensor plus, if applicable, one
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- * remote channel wired to one sensor per CPU.
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- *
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- * Only one thermal zone per AP/CP may trigger interrupts at a time, the
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- * first one that will have a critical trip point will be chosen.
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- */
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- thermal-zones {
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- ap_thermal_ic: ap-thermal-ic {
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- polling-delay-passive = <0>; /* Interrupt driven */
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- polling-delay = <0>; /* Interrupt driven */
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-
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- thermal-sensors = <&ap_thermal 0>;
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-
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- trips {
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- ap_crit: ap-crit {
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- temperature = <100000>; /* mC degrees */
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- hysteresis = <2000>; /* mC degrees */
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- type = "critical";
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- };
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- };
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-
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- cooling-maps { };
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- };
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-
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- ap_thermal_cpu0: ap-thermal-cpu0 {
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- polling-delay-passive = <1000>;
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- polling-delay = <1000>;
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-
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- thermal-sensors = <&ap_thermal 1>;
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-
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- trips {
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- cpu0_hot: cpu0-hot {
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- temperature = <85000>;
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- hysteresis = <2000>;
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- type = "passive";
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- };
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- cpu0_emerg: cpu0-emerg {
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- temperature = <95000>;
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- hysteresis = <2000>;
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- type = "passive";
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- };
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- };
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-
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- cooling-maps {
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- map0_hot: map0-hot {
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- trip = <&cpu0_hot>;
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- cooling-device = <&cpu0 1 2>,
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- <&cpu1 1 2>;
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- };
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- map0_emerg: map0-ermerg {
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- trip = <&cpu0_emerg>;
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- cooling-device = <&cpu0 3 3>,
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- <&cpu1 3 3>;
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- };
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- };
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- };
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-
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- ap_thermal_cpu1: ap-thermal-cpu1 {
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- polling-delay-passive = <1000>;
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- polling-delay = <1000>;
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-
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- thermal-sensors = <&ap_thermal 2>;
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-
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- trips {
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- cpu1_hot: cpu1-hot {
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- temperature = <85000>;
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- hysteresis = <2000>;
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- type = "passive";
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- };
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- cpu1_emerg: cpu1-emerg {
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- temperature = <95000>;
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- hysteresis = <2000>;
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- type = "passive";
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- };
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- };
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-
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- cooling-maps {
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- map1_hot: map1-hot {
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- trip = <&cpu1_hot>;
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- cooling-device = <&cpu0 1 2>,
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- <&cpu1 1 2>;
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- };
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- map1_emerg: map1-emerg {
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- trip = <&cpu1_emerg>;
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- cooling-device = <&cpu0 3 3>,
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- <&cpu1 3 3>;
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- };
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- };
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- };
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-
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- ap_thermal_cpu2: ap-thermal-cpu2 {
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- polling-delay-passive = <1000>;
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- polling-delay = <1000>;
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-
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- thermal-sensors = <&ap_thermal 3>;
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-
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- trips {
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- cpu2_hot: cpu2-hot {
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- temperature = <85000>;
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- hysteresis = <2000>;
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- type = "passive";
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- };
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- cpu2_emerg: cpu2-emerg {
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- temperature = <95000>;
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- hysteresis = <2000>;
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- type = "passive";
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- };
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- };
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-
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- cooling-maps {
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- map2_hot: map2-hot {
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- trip = <&cpu2_hot>;
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- cooling-device = <&cpu2 1 2>,
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- <&cpu3 1 2>;
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- };
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- map2_emerg: map2-emerg {
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- trip = <&cpu2_emerg>;
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- cooling-device = <&cpu2 3 3>,
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- <&cpu3 3 3>;
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- };
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- };
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- };
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-
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- ap_thermal_cpu3: ap-thermal-cpu3 {
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- polling-delay-passive = <1000>;
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- polling-delay = <1000>;
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-
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- thermal-sensors = <&ap_thermal 4>;
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-
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- trips {
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- cpu3_hot: cpu3-hot {
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- temperature = <85000>;
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- hysteresis = <2000>;
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- type = "passive";
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- };
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- cpu3_emerg: cpu3-emerg {
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- temperature = <95000>;
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- hysteresis = <2000>;
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- type = "passive";
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- };
|
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- };
|
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-
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- cooling-maps {
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- map3_hot: map3-bhot {
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- trip = <&cpu3_hot>;
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- cooling-device = <&cpu2 1 2>,
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- <&cpu3 1 2>;
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- };
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- map3_emerg: map3-emerg {
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- trip = <&cpu3_emerg>;
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|
- cooling-device = <&cpu2 3 3>,
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- <&cpu3 3 3>;
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- };
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|
- };
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- };
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|
- };
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};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
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@@ -0,0 +1,456 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (C) 2019 Marvell Technology Group Ltd.
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+ *
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+ * Device Tree file for Marvell Armada AP80x.
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+ */
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+
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/thermal/thermal.h>
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+
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+/dts-v1/;
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+
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+/ {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ aliases {
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+ serial0 = &uart0;
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+ serial1 = &uart1;
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+ gpio0 = &ap_gpio;
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+ spi0 = &spi0;
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+ };
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+
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+ psci {
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+ compatible = "arm,psci-0.2";
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+ method = "smc";
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+ };
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+
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+ reserved-memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ /*
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+ * This area matches the mapping done with a
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+ * mainline U-Boot, and should be updated by the
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+ * bootloader.
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+ */
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+
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+ psci-area@4000000 {
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+ reg = <0x0 0x4000000 0x0 0x200000>;
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+ no-map;
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+ };
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+ };
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+
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+ AP_NAME {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ compatible = "simple-bus";
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+ interrupt-parent = <&gic>;
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+ ranges;
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+
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+ config-space@f0000000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "simple-bus";
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+ ranges = <0x0 0x0 0xf0000000 0x1000000>;
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+
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+ gic: interrupt-controller@210000 {
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+ compatible = "arm,gic-400";
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+ #interrupt-cells = <3>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ interrupt-controller;
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+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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+ reg = <0x210000 0x10000>,
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+ <0x220000 0x20000>,
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+ <0x240000 0x20000>,
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+ <0x260000 0x20000>;
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+
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+ gic_v2m0: v2m@280000 {
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+ compatible = "arm,gic-v2m-frame";
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+ msi-controller;
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+ reg = <0x280000 0x1000>;
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+ arm,msi-base-spi = <160>;
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+ arm,msi-num-spis = <32>;
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+ };
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+ gic_v2m1: v2m@290000 {
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+ compatible = "arm,gic-v2m-frame";
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+ msi-controller;
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+ reg = <0x290000 0x1000>;
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+ arm,msi-base-spi = <192>;
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+ arm,msi-num-spis = <32>;
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+ };
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+ gic_v2m2: v2m@2a0000 {
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+ compatible = "arm,gic-v2m-frame";
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+ msi-controller;
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+ reg = <0x2a0000 0x1000>;
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+ arm,msi-base-spi = <224>;
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+ arm,msi-num-spis = <32>;
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+ };
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+ gic_v2m3: v2m@2b0000 {
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+ compatible = "arm,gic-v2m-frame";
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+ msi-controller;
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+ reg = <0x2b0000 0x1000>;
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+ arm,msi-base-spi = <256>;
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+ arm,msi-num-spis = <32>;
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+ };
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+ };
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+
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+ timer {
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+ compatible = "arm,armv8-timer";
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+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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+ };
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+
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+ pmu {
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+ compatible = "arm,cortex-a72-pmu";
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+ interrupt-parent = <&pic>;
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+ interrupts = <17>;
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+ };
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+
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+ odmi: odmi@300000 {
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+ compatible = "marvell,odmi-controller";
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+ interrupt-controller;
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+ msi-controller;
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+ marvell,odmi-frames = <4>;
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+ reg = <0x300000 0x4000>,
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+ <0x304000 0x4000>,
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+ <0x308000 0x4000>,
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+ <0x30C000 0x4000>;
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+ marvell,spi-base = <128>, <136>, <144>, <152>;
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+ };
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+
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+ gicp: gicp@3f0040 {
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+ compatible = "marvell,ap806-gicp";
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+ reg = <0x3f0040 0x10>;
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+ marvell,spi-ranges = <64 64>, <288 64>;
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+ msi-controller;
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+ };
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+
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+ pic: interrupt-controller@3f0100 {
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+ compatible = "marvell,armada-8k-pic";
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+ reg = <0x3f0100 0x10>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ sei: interrupt-controller@3f0200 {
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+ compatible = "marvell,ap806-sei";
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+ reg = <0x3f0200 0x40>;
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+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ msi-controller;
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+ };
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+
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+ xor@400000 {
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+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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+ reg = <0x400000 0x1000>,
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+ <0x410000 0x1000>;
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+ msi-parent = <&gic_v2m0>;
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+ clocks = <&ap_clk 3>;
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+ dma-coherent;
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+ };
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+
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+ xor@420000 {
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+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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+ reg = <0x420000 0x1000>,
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+ <0x430000 0x1000>;
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+ msi-parent = <&gic_v2m0>;
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+ clocks = <&ap_clk 3>;
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+ dma-coherent;
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+ };
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+
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+ xor@440000 {
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+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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+ reg = <0x440000 0x1000>,
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+ <0x450000 0x1000>;
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+ msi-parent = <&gic_v2m0>;
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+ clocks = <&ap_clk 3>;
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+ dma-coherent;
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+ };
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+
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+ xor@460000 {
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+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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+ reg = <0x460000 0x1000>,
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+ <0x470000 0x1000>;
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+ msi-parent = <&gic_v2m0>;
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+ clocks = <&ap_clk 3>;
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+ dma-coherent;
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+ };
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+
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+ spi0: spi@510600 {
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+ compatible = "marvell,armada-380-spi";
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+ reg = <0x510600 0x50>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ap_clk 3>;
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+ status = "disabled";
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+ };
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+
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+ i2c0: i2c@511000 {
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+ compatible = "marvell,mv78230-i2c";
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+ reg = <0x511000 0x20>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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+ timeout-ms = <1000>;
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+ clocks = <&ap_clk 3>;
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+ status = "disabled";
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+ };
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+
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+ uart0: serial@512000 {
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+ compatible = "snps,dw-apb-uart";
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+ reg = <0x512000 0x100>;
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+ reg-shift = <2>;
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+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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+ reg-io-width = <1>;
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+ clocks = <&ap_clk 3>;
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+ status = "disabled";
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+ };
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+
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+ uart1: serial@512100 {
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+ compatible = "snps,dw-apb-uart";
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+ reg = <0x512100 0x100>;
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+ reg-shift = <2>;
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+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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+ reg-io-width = <1>;
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+ clocks = <&ap_clk 3>;
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+ status = "disabled";
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+
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+ };
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+
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+ watchdog: watchdog@610000 {
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+ compatible = "arm,sbsa-gwdt";
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+ reg = <0x610000 0x1000>, <0x600000 0x1000>;
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+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ ap_sdhci0: sdhci@6e0000 {
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+ compatible = "marvell,armada-ap806-sdhci";
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+ reg = <0x6e0000 0x300>;
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+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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+ clock-names = "core";
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+ clocks = <&ap_clk 4>;
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+ dma-coherent;
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+ marvell,xenon-phy-slow-mode;
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+ status = "disabled";
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+ };
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+
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+ ap_syscon0: system-controller@6f4000 {
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+ compatible = "syscon", "simple-mfd";
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+ reg = <0x6f4000 0x2000>;
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+
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+ ap_clk: clock {
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+ compatible = "marvell,ap806-clock";
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+ #clock-cells = <1>;
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+ };
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+
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+ ap_pinctrl: pinctrl {
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+ compatible = "marvell,ap806-pinctrl";
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+
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+ uart0_pins: uart0-pins {
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+ marvell,pins = "mpp11", "mpp19";
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+ marvell,function = "uart0";
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+ };
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+ };
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+
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+ ap_gpio: gpio@1040 {
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+ compatible = "marvell,armada-8k-gpio";
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+ offset = <0x1040>;
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+ ngpios = <20>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ gpio-ranges = <&ap_pinctrl 0 0 20>;
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+ };
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+ };
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+
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+ ap_syscon1: system-controller@6f8000 {
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+ compatible = "syscon", "simple-mfd";
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+ reg = <0x6f8000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ cpu_clk: clock-cpu@278 {
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+ compatible = "marvell,ap806-cpu-clock";
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+ clocks = <&ap_clk 0>, <&ap_clk 1>;
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+ #clock-cells = <1>;
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+ reg = <0x278 0xa30>;
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+ };
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+
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+ ap_thermal: thermal-sensor@80 {
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+ compatible = "marvell,armada-ap806-thermal";
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+ reg = <0x80 0x10>;
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+ interrupt-parent = <&sei>;
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+ interrupts = <18>;
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+ #thermal-sensor-cells = <1>;
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+ };
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+ };
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+ };
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+ };
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+
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+ /*
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+ * The thermal IP features one internal sensor plus, if applicable, one
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+ * remote channel wired to one sensor per CPU.
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+ *
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+ * Only one thermal zone per AP/CP may trigger interrupts at a time, the
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+ * first one that will have a critical trip point will be chosen.
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+ */
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+ thermal-zones {
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+ ap_thermal_ic: ap-thermal-ic {
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+ polling-delay-passive = <0>; /* Interrupt driven */
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+ polling-delay = <0>; /* Interrupt driven */
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+
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+ thermal-sensors = <&ap_thermal 0>;
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+
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+ trips {
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+ ap_crit: ap-crit {
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+ temperature = <100000>; /* mC degrees */
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+ hysteresis = <2000>; /* mC degrees */
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+ type = "critical";
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+ };
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+ };
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+
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+ cooling-maps { };
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+ };
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+
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+ ap_thermal_cpu0: ap-thermal-cpu0 {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&ap_thermal 1>;
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+
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+ trips {
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+ cpu0_hot: cpu0-hot {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+ cpu0_emerg: cpu0-emerg {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map0_hot: map0-hot {
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+ trip = <&cpu0_hot>;
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+ cooling-device = <&cpu0 1 2>,
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+ <&cpu1 1 2>;
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+ };
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+ map0_emerg: map0-ermerg {
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+ trip = <&cpu0_emerg>;
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+ cooling-device = <&cpu0 3 3>,
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+ <&cpu1 3 3>;
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+ };
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+ };
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+ };
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+
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+ ap_thermal_cpu1: ap-thermal-cpu1 {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&ap_thermal 2>;
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+
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+ trips {
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+ cpu1_hot: cpu1-hot {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+ cpu1_emerg: cpu1-emerg {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map1_hot: map1-hot {
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+ trip = <&cpu1_hot>;
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+ cooling-device = <&cpu0 1 2>,
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+ <&cpu1 1 2>;
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+ };
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+ map1_emerg: map1-emerg {
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+ trip = <&cpu1_emerg>;
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+ cooling-device = <&cpu0 3 3>,
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+ <&cpu1 3 3>;
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+ };
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+ };
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+ };
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+
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+ ap_thermal_cpu2: ap-thermal-cpu2 {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&ap_thermal 3>;
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+
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+ trips {
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+ cpu2_hot: cpu2-hot {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+ cpu2_emerg: cpu2-emerg {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map2_hot: map2-hot {
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+ trip = <&cpu2_hot>;
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+ cooling-device = <&cpu2 1 2>,
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+ <&cpu3 1 2>;
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+ };
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+ map2_emerg: map2-emerg {
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+ trip = <&cpu2_emerg>;
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+ cooling-device = <&cpu2 3 3>,
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+ <&cpu3 3 3>;
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+ };
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+ };
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+ };
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+
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+ ap_thermal_cpu3: ap-thermal-cpu3 {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&ap_thermal 4>;
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+
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+ trips {
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+ cpu3_hot: cpu3-hot {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+ cpu3_emerg: cpu3-emerg {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map3_hot: map3-bhot {
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+ trip = <&cpu3_hot>;
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+ cooling-device = <&cpu2 1 2>,
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+ <&cpu3 1 2>;
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+ };
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+ map3_emerg: map3-emerg {
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+ trip = <&cpu3_emerg>;
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+ cooling-device = <&cpu2 3 3>,
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+ <&cpu3 3 3>;
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+ };
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+ };
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+ };
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+ };
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+};
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