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bb1eb5e8e6
1. Add support for Marvell CN9130 SoC
2. Add support for CP115,and create an armada-cp11x.dtsi file which will be used to instantiate both CP110 and CP115
3. Add support for AP807/AP807-quad,AP807 is a major component of CN9130 SoC series
4. Drop PCIe I/O ranges from CP11x file and externalize PCIe macros from CP11x file
Signed-off-by: Ian Chang <ianchang@ieiworld.com>
(cherry picked from commit c98ddf0f01)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
56 lines
1.6 KiB
Diff
56 lines
1.6 KiB
Diff
From 6b8970bd8d7a17a648e31f3996d9b21336b4a2cf Mon Sep 17 00:00:00 2001
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From: Miquel Raynal <miquel.raynal@bootlin.com>
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Date: Fri, 4 Oct 2019 16:27:35 +0200
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Subject: [PATCH] arm64: dts: marvell: Add support for Marvell CN9130 SoC
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support
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A CN9130 SoC has one AP807 and one internal CP115.
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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---
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arch/arm64/boot/dts/marvell/cn9130.dtsi | 37 +++++++++++++++++++++++++
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1 file changed, 37 insertions(+)
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create mode 100644 arch/arm64/boot/dts/marvell/cn9130.dtsi
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--- /dev/null
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+++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi
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@@ -0,0 +1,37 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (C) 2019 Marvell International Ltd.
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+ *
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+ * Device tree for the CN9130 SoC.
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+ */
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+
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+#include "armada-ap807-quad.dtsi"
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+
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+/ {
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+ model = "Marvell Armada CN9130 SoC";
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+ compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
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+ "marvell,armada-ap807";
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+};
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+
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+/*
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+ * Instantiate the internal CP115
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+ */
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+
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+#define CP11X_NAME cp0
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+#define CP11X_BASE f2000000
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+#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
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+ 0xe0000000 + ((iface - 1) * 0x1000000))
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+#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
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+#define CP11X_PCIE0_BASE f2600000
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+#define CP11X_PCIE1_BASE f2620000
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+#define CP11X_PCIE2_BASE f2640000
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+
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+#include "armada-cp115.dtsi"
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+
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+#undef CP11X_NAME
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+#undef CP11X_BASE
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+#undef CP11X_PCIEx_MEM_BASE
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+#undef CP11X_PCIEx_MEM_SIZE
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+#undef CP11X_PCIE0_BASE
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+#undef CP11X_PCIE1_BASE
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+#undef CP11X_PCIE2_BASE
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