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2d5ee43dc6
Manually rebased generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch All others updated automatically. Compile-tested on: ramips/mt7621, armvirt/32 Runtime-tested on: ramips/mt7621, armvirt/32 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
128 lines
3.7 KiB
Diff
128 lines
3.7 KiB
Diff
From d9d113c22c634219cc248a7c6dcf157e2927edad Mon Sep 17 00:00:00 2001
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From: Fugang Duan <fugang.duan@nxp.com>
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Date: Tue, 23 Jul 2019 11:36:22 +0800
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Subject: [PATCH] MLK-21445 serial: fsl_lpuart: do HW reset for communication
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port
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Do HW reset for communication port after the port is registered
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if the UART controller support the feature.
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Do partition reset with LPUART's power on, LPUART registers will
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keep the previous status, like on i.MX8QM platform, which is not
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expected action, so reset the HW is required.
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Currently, only i.MX7ULP and i.MX8QM LPUART controllers include
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global register that support HW reset.
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Tested-by: Robin Gong <yibin.gong@nxp.com>
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Tested-by: Peng Fan <peng.fan@nxp.com>
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Reviewed-by: Robby Cai <robby.cai@nxp.com>
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Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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(cherry picked from commit c2bc1f62ec28981462c9cb5ceac17134931ca19f)
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Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
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Signed-off-by: Shrikant Bobade <Shrikant_Bobade@mentor.com>
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(cherry picked from commit 9f396f540093402317c3c1b9a8fe955b91c89164)
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---
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drivers/tty/serial/fsl_lpuart.c | 48 +++++++++++++++++++++++++++++++++++++++++
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1 file changed, 48 insertions(+)
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--- a/drivers/tty/serial/fsl_lpuart.c
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+++ b/drivers/tty/serial/fsl_lpuart.c
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@@ -11,6 +11,7 @@
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#include <linux/clk.h>
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#include <linux/console.h>
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+#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/dmapool.h>
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@@ -116,6 +117,11 @@
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#define UARTSFIFO_TXOF 0x02
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#define UARTSFIFO_RXUF 0x01
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+/* 32-bit global registers only for i.MX7ulp/MX8x
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+ * The driver only use the reset feature to reset HW.
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+ */
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+#define UART_GLOBAL 0x8
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+
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/* 32-bit register definition */
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#define UARTBAUD 0x00
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#define UARTSTAT 0x04
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@@ -230,6 +236,10 @@
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#define UARTWATER_TXWATER_OFF 0
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#define UARTWATER_RXWATER_OFF 16
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+#define UART_GLOBAL_RST 0x2
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+#define RST_HW_MIN_US 20
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+#define RST_HW_MAX_US 40
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+
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#define UARTFIFO_RXIDEN_RDRF 0x3
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#define UARTCTRL_IDLECFG 0x7
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@@ -350,6 +360,11 @@ static inline bool is_layerscape_lpuart(
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sport->devtype == LS1028A_LPUART);
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}
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+static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport)
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+{
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+ return sport->devtype == IMX7ULP_LPUART;
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+}
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+
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static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
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{
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return sport->devtype == IMX8QXP_LPUART;
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@@ -413,6 +428,33 @@ static unsigned int lpuart_get_baud_clk_
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#define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
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#define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
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+static int lpuart_hw_reset(struct lpuart_port *sport)
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+{
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+ struct uart_port *port = &sport->port;
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+ void __iomem *global_addr;
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+ int ret;
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+
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+ if (uart_console(port))
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+ return 0;
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+
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+ ret = clk_prepare_enable(sport->ipg_clk);
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+ if (ret) {
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+ dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
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+ return ret;
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+ }
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+
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+ if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
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+ global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
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+ writel(UART_GLOBAL_RST, global_addr);
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+ usleep_range(RST_HW_MIN_US, RST_HW_MAX_US);
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+ writel(0, global_addr);
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+ usleep_range(RST_HW_MIN_US, RST_HW_MAX_US);
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+ }
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+
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+ clk_disable_unprepare(sport->ipg_clk);
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+ return 0;
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+}
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+
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static void lpuart_stop_tx(struct uart_port *port)
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{
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unsigned char temp;
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@@ -2731,6 +2773,10 @@ static int lpuart_probe(struct platform_
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if (ret)
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goto failed_attach_port;
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+ ret = lpuart_hw_reset(sport);
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+ if (ret)
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+ goto failed_reset;
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+
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uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
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if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
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@@ -2754,6 +2800,8 @@ static int lpuart_probe(struct platform_
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return 0;
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+failed_reset:
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+ uart_remove_one_port(&lpuart_reg, &sport->port);
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failed_attach_port:
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failed_irq_request:
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lpuart_disable_clks(sport);
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