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https://github.com/openwrt/openwrt.git
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5632227f44
Hardware specification:
SoC: MediaTek MT7986A 4x A53
Flash: ESMT F50L1G41LB 128MB
RAM: W632GU6NB DDR3 256MB
Ethernet: 1x 2.5G + 4x 1G
WiFi1: MT7975N 2.4GHz 4T4R
WiFi2: MT7975PN 5GHz 4T4R
Button: Reset, WPS
Power: DC 12V 2A
Flash instructions:
1. Connect to the router using ssh or telnet,
username: useradmin, password is the web
login password of the router.
2. Use scp to upload bl31-uboot.fip and flash:
"mtd write xxx-preloader.bin spi0.0"
"mtd write xxx-bl31-uboot.fip FIP"
"mtd erase ubi"
3. Connect to the router via the Lan port,
set a static ip of your PC.
(ip 192.168.1.254, gateway 192.168.1.1)
4. Download initramfs image, reboot router,
waiting for tftp recovery to complete.
5. After openwrt boots up, perform sysupgrade.
Note:
1. Back up all mtd partitions before flashing.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
(cherry picked from commit 4ae474afbd
)
285 lines
4.7 KiB
Plaintext
285 lines
4.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "mt7986a.dtsi"
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/ {
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model = "Netcore N60";
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compatible = "netcore,n60", "mediatek,mt7986a";
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aliases {
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serial0 = &uart0;
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label-mac-device = &gmac0;
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led-boot = &led_status_red;
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led-failsafe = &led_status_red;
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led-running = &led_status_blue;
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led-upgrade = &led_status_blue;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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reg = <0 0x40000000 0 0x10000000>;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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};
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mesh {
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label = "mesh";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_status_red: status-red {
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_STATUS;
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gpios = <&pio 29 GPIO_ACTIVE_LOW>;
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};
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led_status_blue: status-blue {
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_STATUS;
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gpios = <&pio 32 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&crypto {
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status = "okay";
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "2500base-x";
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nvmem-cells = <&macaddr_lan>;
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nvmem-cell-names = "mac-address";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-handle = <&phy6>;
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phy-mode = "2500base-x";
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nvmem-cells = <&macaddr_wan>;
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nvmem-cell-names = "mac-address";
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&mdio {
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reset-delay-us = <600>;
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reset-post-delay-us = <20000>;
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reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
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phy6: phy@6 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <6>;
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mxl,led-config = <0x0 0x0 0x0 0x3f0>;
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};
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switch: switch@1f {
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compatible = "mediatek,mt7531";
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reg = <31>;
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reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&pio>;
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interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&switch {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_flash_pins>;
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status = "okay";
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flash@0 {
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compatible = "spi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <20000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "BL2";
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reg = <0x0000000 0x0100000>;
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read-only;
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};
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partition@100000 {
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label = "u-boot-env";
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reg = <0x0100000 0x0080000>;
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};
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factory: partition@180000 {
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label = "Factory";
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reg = <0x0180000 0x0200000>;
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read-only;
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};
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partition@380000 {
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label = "FIP";
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reg = <0x0380000 0x0200000>;
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read-only;
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};
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partition@580000 {
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label = "ubi";
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reg = <0x0580000 0x7280000>;
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};
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};
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};
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};
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&pio {
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spi_flash_pins: spi-flash-pins-33-to-38 {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
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drive-strength = <8>;
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mediatek,pull-up-adv = <0>; /* bias-disable */
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};
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conf-pd {
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pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
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drive-strength = <8>;
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mediatek,pull-down-adv = <0>; /* bias-disable */
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};
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};
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wf_2g_5g_pins: wf_2g_5g-pins {
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mux {
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function = "wifi";
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groups = "wf_2g", "wf_5g";
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};
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conf {
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pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
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"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
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"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
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"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
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"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
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"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
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"WF1_TOP_CLK", "WF1_TOP_DATA";
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drive-strength = <4>;
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};
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};
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};
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&trng {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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&wifi {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&wf_2g_5g_pins>;
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mediatek,mtd-eeprom = <&factory 0x0>;
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};
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&factory {
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_lan: macaddr@1fef20 {
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reg = <0x1fef20 0x6>;
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};
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macaddr_wan: macaddr@1fef26 {
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reg = <0x1fef26 0x6>;
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};
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};
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};
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