mirror of
https://github.com/openwrt/openwrt.git
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301 lines
8.5 KiB
Diff
301 lines
8.5 KiB
Diff
--- a/arch/mips/ath79/mach-ap136.c
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+++ b/arch/mips/ath79/mach-ap136.c
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@@ -18,23 +18,29 @@
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*
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*/
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-#include <linux/pci.h>
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-#include <linux/ath9k_platform.h>
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+#include <linux/platform_device.h>
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+#include <linux/ar8216_platform.h>
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-#include "machtypes.h"
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+#include <asm/mach-ath79/ar71xx_regs.h>
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+
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+#include "common.h"
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+#include "pci.h"
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+#include "dev-ap9x-pci.h"
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#include "dev-gpio-buttons.h"
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+#include "dev-eth.h"
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#include "dev-leds-gpio.h"
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-#include "dev-spi.h"
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+#include "dev-m25p80.h"
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+#include "dev-nfc.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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-#include "pci.h"
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+#include "machtypes.h"
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-#define AP136_GPIO_LED_STATUS_RED 14
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-#define AP136_GPIO_LED_STATUS_GREEN 19
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#define AP136_GPIO_LED_USB 4
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-#define AP136_GPIO_LED_WLAN_2G 13
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#define AP136_GPIO_LED_WLAN_5G 12
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+#define AP136_GPIO_LED_WLAN_2G 13
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+#define AP136_GPIO_LED_STATUS_RED 14
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#define AP136_GPIO_LED_WPS_RED 15
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+#define AP136_GPIO_LED_STATUS_GREEN 19
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#define AP136_GPIO_LED_WPS_GREEN 20
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#define AP136_GPIO_BTN_WPS 16
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@@ -43,37 +49,39 @@
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#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
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#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
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-#define AP136_WMAC_CALDATA_OFFSET 0x1000
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-#define AP136_PCIE_CALDATA_OFFSET 0x5000
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+#define AP136_MAC0_OFFSET 0
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+#define AP136_MAC1_OFFSET 6
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+#define AP136_WMAC_CALDATA_OFFSET 0x1000
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+#define AP136_PCIE_CALDATA_OFFSET 0x5000
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static struct gpio_led ap136_leds_gpio[] __initdata = {
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{
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- .name = "qca:green:status",
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+ .name = "ap136:green:status",
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.gpio = AP136_GPIO_LED_STATUS_GREEN,
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.active_low = 1,
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},
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{
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- .name = "qca:red:status",
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+ .name = "ap136:red:status",
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.gpio = AP136_GPIO_LED_STATUS_RED,
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.active_low = 1,
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},
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{
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- .name = "qca:green:wps",
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+ .name = "ap136:green:wps",
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.gpio = AP136_GPIO_LED_WPS_GREEN,
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.active_low = 1,
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},
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{
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- .name = "qca:red:wps",
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+ .name = "ap136:red:wps",
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.gpio = AP136_GPIO_LED_WPS_RED,
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.active_low = 1,
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},
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{
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- .name = "qca:red:wlan-2g",
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+ .name = "ap136:red:wlan-2g",
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.gpio = AP136_GPIO_LED_WLAN_2G,
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.active_low = 1,
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},
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{
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- .name = "qca:red:usb",
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+ .name = "ap136:red:usb",
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.gpio = AP136_GPIO_LED_USB,
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.active_low = 1,
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}
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@@ -98,59 +106,151 @@ static struct gpio_keys_button ap136_gpi
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},
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};
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-static struct spi_board_info ap136_spi_info[] = {
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- {
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- .bus_num = 0,
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- .chip_select = 0,
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- .max_speed_hz = 25000000,
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- .modalias = "mx25l6405d",
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- }
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+static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
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+static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
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+
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+static struct ar8327_platform_data ap136_ar8327_data = {
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+ .pad0_cfg = &ap136_ar8327_pad0_cfg,
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+ .pad6_cfg = &ap136_ar8327_pad6_cfg,
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+ .port0_cfg = {
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+ .force_link = 1,
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+ .speed = AR8327_PORT_SPEED_1000,
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+ .duplex = 1,
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+ .txpause = 1,
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+ .rxpause = 1,
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+ },
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+ .port6_cfg = {
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+ .force_link = 1,
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+ .speed = AR8327_PORT_SPEED_1000,
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+ .duplex = 1,
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+ .txpause = 1,
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+ .rxpause = 1,
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+ },
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};
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-static struct ath79_spi_platform_data ap136_spi_data = {
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- .bus_num = 0,
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- .num_chipselect = 1,
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+static struct mdio_board_info ap136_mdio0_info[] = {
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+ {
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+ .bus_id = "ag71xx-mdio.0",
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+ .phy_addr = 0,
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+ .platform_data = &ap136_ar8327_data,
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+ },
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};
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-#ifdef CONFIG_PCI
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-static struct ath9k_platform_data ap136_ath9k_data;
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+static void __init ap136_common_setup(void)
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+{
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+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
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+ ath79_register_m25p80(NULL);
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+
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+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
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+ ap136_leds_gpio);
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+ ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
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+ ARRAY_SIZE(ap136_gpio_keys),
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+ ap136_gpio_keys);
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+
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+ ath79_register_usb();
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+ ath79_register_nfc();
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+
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+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
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+
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+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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+
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+ ath79_register_mdio(0, 0x0);
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+ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
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+
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+ mdiobus_register_board_info(ap136_mdio0_info,
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+ ARRAY_SIZE(ap136_mdio0_info));
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+
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+ /* GMAC0 is connected to the RMGII interface */
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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+ ath79_eth0_data.phy_mask = BIT(0);
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+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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+
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+ ath79_register_eth(0);
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+
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+ /* GMAC1 is connected tot eh SGMII interface */
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+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
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+ ath79_eth1_data.speed = SPEED_1000;
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+ ath79_eth1_data.duplex = DUPLEX_FULL;
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+
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+ ath79_register_eth(1);
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+}
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+
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+static void __init ap136_010_setup(void)
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{
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- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
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- dev->dev.platform_data = &ap136_ath9k_data;
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+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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- return 0;
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+ /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
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+ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
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+ ap136_ar8327_pad0_cfg.txclk_delay_en = true;
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+ ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
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+ ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
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+ ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
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+
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+ /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */
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+ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
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+ ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
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+ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
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+
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+ ath79_eth0_pll_data.pll_1000 = 0xa6000000;
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+ ath79_eth1_pll_data.pll_1000 = 0x03000101;
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+
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+ ap136_common_setup();
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+ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
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}
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-static void __init ap136_pci_init(u8 *eeprom)
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+MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
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+ "Atheros AP136-010 reference board",
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+ ap136_010_setup);
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+
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+static void __init ap136_020_common_setup(void)
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{
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- memcpy(ap136_ath9k_data.eeprom_data, eeprom,
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- sizeof(ap136_ath9k_data.eeprom_data));
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+ /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
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+ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
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+ ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
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- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
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- ath79_register_pci();
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+ /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
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+ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
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+ ap136_ar8327_pad6_cfg.txclk_delay_en = true;
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+ ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
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+ ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
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+ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
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+
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+ ath79_eth0_pll_data.pll_1000 = 0x56000000;
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+ ath79_eth1_pll_data.pll_1000 = 0x03000101;
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+
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+ ap136_common_setup();
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}
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-#else
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-static inline void ap136_pci_init(u8 *eeprom) {}
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-#endif /* CONFIG_PCI */
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-static void __init ap136_setup(void)
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+static void __init ap136_020_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
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- ap136_leds_gpio);
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- ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
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- ARRAY_SIZE(ap136_gpio_keys),
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- ap136_gpio_keys);
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- ath79_register_spi(&ap136_spi_data, ap136_spi_info,
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- ARRAY_SIZE(ap136_spi_info));
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- ath79_register_usb();
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- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
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- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
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+ ap136_020_common_setup();
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+ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
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}
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-MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
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- "Atheros AP136-010 reference board",
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- ap136_setup);
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+MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
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+ "Atheros AP136-020 reference board",
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+ ap136_020_setup);
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+
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+/*
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+ * AP135-020 is similar to AP136-020, any future AP135 specific init
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+ * code can be added here.
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+ */
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+static void __init ap135_020_setup(void)
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+{
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+ ap136_leds_gpio[0].name = "ap135:green:status";
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+ ap136_leds_gpio[1].name = "ap135:red:status";
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+ ap136_leds_gpio[2].name = "ap135:green:wps";
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+ ap136_leds_gpio[3].name = "ap135:red:wps";
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+ ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
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+ ap136_leds_gpio[5].name = "ap135:red:usb";
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+
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+ ap136_020_common_setup();
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+ ath79_register_pci();
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+}
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+
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+MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",
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+ "Atheros AP135-020 reference board",
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+ ap135_020_setup);
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -16,16 +16,17 @@ config ATH79_MACH_AP121
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Atheros AP121 reference board.
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config ATH79_MACH_AP136
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- bool "Atheros AP136 reference board"
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+ bool "Atheros AP136/AP135 reference board"
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select SOC_QCA955X
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select ATH79_DEV_GPIO_BUTTONS
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select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_NFC
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select ATH79_DEV_SPI
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select ATH79_DEV_USB
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select ATH79_DEV_WMAC
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help
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Say 'Y' here if you want your kernel to support the
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- Atheros AP136 reference board.
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+ Atheros AP136 or AP135 reference boards.
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config ATH79_MACH_AP81
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bool "Atheros AP81 reference board"
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